Conflict Between Ocr Write And Compare-Match; Figure 11.19 Conflict Between Ocr Write And Compare-Match (When Automatic Addition Function Is Not Used) - Renesas H8S Series Hardware Manual

11.7.3

Conflict between OCR Write and Compare-Match

If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of
conflict.
Figure 11.19 Conflict between OCR Write and Compare-Match
Write cycle of OCR
T 1
φ
Address OCR address
Internal write
signal
FRC
OCR
Compare-match
signal
(When Automatic Addition Function is Not Used)
Section 11 16-Bit Free-Running Timer (FRT)
T 2
N N + 1
N M
Write data
Disabled
Rev. 3.00 Jul. 14, 2005 Page 301 of 986
REJ09B0098-0300