Module Stop Mode; Direct Transitions - Renesas H8S Series Hardware Manual

Section 24 Power-Down Modes
24.10

Module Stop Mode

Module stop mode can be individually set for each on-chip peripheral module.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. In turn, when the corresponding
MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of
the bus cycle. In module stop mode, the internal states of on-chip peripheral modules other than
the SCI, PWM, PWMX, and A/D converter are retained.
After the reset state is cancelled, all on-chip peripheral modules other than the DTC are in module
stop mode.
While an on-chip peripheral module is in module stop mode, its registers cannot be read from or
written to.
24.11

Direct Transitions

The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a
direct transition is made from high-speed mode to subactive mode and vice versa, there is no
interruption of program execution. A direct transition is enabled by executing the SLEEP
instruction after setting the DTON bit in LPWRCR to 1. After a transition, direct transition
exception handling starts.
When the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to
1, the LSON bit and DTON bit in LPWRCR both set to 1, and the PSS bit in TSCR (WDT_1) set
to 1, the CPU makes a direct transition to subactive mode.
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR set to 1,
the LSON bit in LPWRCR cleared to 0, the DTON bit in LPWRCR set to 1, and the PSS bit in
TSCR (WDT_1) set to 1, after the time set in the STS2 to STS0 bits in SBYCR has elapsed, the
CPU makes a direct transition to high-speed mode.
Rev. 3.00 Jul. 14, 2005 Page 878 of 986
REJ09B0098-0300