Interrupt Exception Handling; Trap Instruction Exception Handling; Table 4.4 Status Of Ccr After Trap Instruction Exception Handling - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Section 4 Exception Handling

Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The sources to start interrupt exception

handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to

WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt

with the highest priority. For details, see section 5, Interrupt Controller.

Interrupt exception handling is conducted as follows:

1. The values in the program counter (PC) and condition code register (CCR) are saved in the

2. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

Trap instruction exception handling is conducted as follows:

1. The values in the program counter (PC) and condition code register (CCR) are saved in the

2. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4.4 shows the status of CCR after execution of trap instruction exception handling.

Status of CCR after Trap Instruction Exception Handling

Interrupt Control Mode

Rev. 3.00 Jul. 14, 2005 Page 76 of 986

REJ09B0098-0300

Retains value prior to execution

H8s/2100 series H8s/2114r R4f2114r