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Renesas H8S/2100 Series Manuals
Manuals and User Guides for Renesas H8S/2100 Series. We have
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Renesas H8S/2100 Series manuals available for free PDF download: Hardware Manual
Renesas H8S/2100 Series Hardware Manual (1038 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.77 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
Table of Contents
11
Section 1 Overview
49
Overview
49
Section 1 Overview
50
Internal Block Diagram
51
Figure 1.1 H8S/2114R Group Internal Block Diagram
51
Pin Description
52
Pin Arrangement
52
Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)
52
Pin Arrangement in each Operating Mode
53
Table 1.1 H8S/2114R Group Pin Arrangement in each Operating Mode
53
Overview
53
Pin Functions
58
Table 1.2 Pin Functions
58
Electrical Characteristics
59
Figure 1.3 Sample Design of Reset Signals with no Affection each Other
65
Section 2 CPU
67
Features
67
Differences between H8S/2600 CPU and H8S/2000 CPU
68
Differences from H8/300 CPU
69
Differences from H8/300H CPU
69
CPU Operating Modes
70
Normal Mode
70
Figure 2.1 Exception Vector Table (Normal Mode)
71
Figure 2.2 Stack Structure in Normal Mode
71
Advanced Mode
72
Figure 2.3 Exception Vector Table (Advanced Mode)
72
Figure 2.4 Stack Structure in Advanced Mode
73
Address Space
74
Figure 2.5 Memory Map
74
Register Configuration
75
Figure 2.6 CPU Internal Registers
75
Figure 2.7 Usage of General Registers
76
General Registers
76
Extended Control Register (EXR)
77
Figure 2.8 Stack
77
Program Counter (PC)
77
Condition-Code Register (CCR)
78
Initial Register Values
79
Data Formats
80
General Register Data Formats
80
Figure 2.9 General Register Data Formats (1)
80
Figure 2.9 General Register Data Formats (2)
81
Memory Data Formats
82
Figure 2.10 Memory Data Formats
82
Instruction Set
83
Table 2.1 Instruction Classification
83
Table 2.2 Operation Notation
84
Table of Instructions Classified by Function
84
Table 2.3 Data Transfer Instructions
85
Table 2.4 Arithmetic Operations Instructions (1)
86
Table 2.4 Arithmetic Operations Instructions (2)
87
Table 2.5 Logic Operations Instructions
88
Table 2.6 Shift Instructions
89
Table 2.7 Bit Manipulation Instructions (1)
90
Table 2.7 Bit Manipulation Instructions (2)
91
Table 2.8 Branch Instructions
92
Table 2.9 System Control Instructions
93
Table 2.10 Block Data Transfer Instructions
94
Basic Instruction Formats
95
Figure 2.11 Instruction Formats (Examples)
95
Addressing Modes and Effective Address Calculation
96
Register Direct-Rn
96
Register Indirect-@Ern
96
Table 2.11 Addressing Modes
96
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
97
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
97
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
97
Immediate-#XX:8, #XX:16, or #XX:32
98
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
98
Table 2.12 Absolute Address Access Ranges
98
Memory Indirect-@@Aa:8
99
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
99
Effective Address Calculation
100
Table 2.13 Effective Address Calculation (1)
100
Table 2.13 Effective Address Calculation (2)
101
Processing States
102
Figure 2.13 State Transitions
103
Usage Notes
104
Note on TAS Instruction Usage
104
Note on STM/LDM Instruction Usage
104
Note on Bit Manipulation Instructions
104
EEPMOV Instruction
105
Section 3 MCU Operating Modes
107
Operating Mode Selection
107
Register Descriptions
108
Mode Control Register (MDCR)
108
System Control Register (SYSCR)
109
Serial Timer Control Register (STCR)
111
System Control Register 3 (SYSCR3)
114
Operating Mode Descriptions
115
Mode 2
115
Mode 3
115
Address Map
115
Figure 3.1 Address Map
116
Section 4 Exception Handling
117
Exception Handling Types and Priority
117
Table 4.1 Exception Types and Priority
117
Exception Sources and Exception Vector Table
118
Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode)
118
Table 4.3 Exception Handling Vector Table (Extended Vector Mode)
120
Reset
122
Reset Exception Handling
122
Interrupts Immediately after Reset
123
On-Chip Peripheral Modules after Reset Is Cancelled
123
Figure 4.1 Reset Sequence (Mode 2)
123
Interrupt Exception Handling
124
Trap Instruction Exception Handling
124
Table 4.4 Status of CCR after Trap Instruction Exception Handling
124
Stack Status after Exception Handling
125
Figure 4.2 Stack Status after Exception Handling
125
Usage Note
126
Figure 4.3 Operation When SP Value Is Odd
126
Section 5 Interrupt Controller
127
Features
127
Figure 5.1 Block Diagram of Interrupt Controller
128
Input/Output Pins
129
Table 5.1 Pin Configuration
129
Register Descriptions
130
Interrupt Control Registers a to D (ICRA to ICRD)
131
Table 5.2 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0)
131
Table 5.3 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1)
132
Address Break Control Register (ABRKCR)
133
Break Address Registers a to C (BARA to BARC)
134
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
135
IRQ Enable Registers (IER16, IER)
138
IRQ Status Registers (ISR16, ISR)
139
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)
141
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts
143
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (Extended Vector Mode: EIVS = 1)
144
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
145
Interrupt Sources
147
External Interrupt Sources
147
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0
148
Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)
149
Internal Interrupt Sources
150
Interrupt Exception Handling Vector Tables
150
Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode)
151
Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode)
154
Interrupt Control Modes and Interrupt Operation
157
Table 5.6 Interrupt Control Modes
157
Figure 5.6 Block Diagram of Interrupt Control Operation
158
Table 5.7 Interrupts Selected in each Interrupt Control Mode
159
Interrupt Control Mode 0
160
Table 5.8 Operations and Control Signal Functions in each Interrupt Control Mode
160
Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
161
Figure 5.8 State Transition in Interrupt Control Mode 1
162
Interrupt Control Mode 1
162
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1
164
Interrupt Exception Handling Sequence
165
Figure 5.10 Interrupt Exception Handling
166
Interrupt Response Times
167
Table 5.9 Interrupt Response Times
167
DTC Activation by Interrupt
168
Figure 5.11 Interrupt Control for DTC
168
Table 5.10 Interrupt Source Selection and Clearing Control
169
Address Breaks
170
Features
170
Block Diagram
170
Figure 5.12 Block Diagram of Address Break Function
170
Operation
171
Usage Notes
171
Figure 5.13 Examples of Address Break Timing
172
Usage Notes
173
Conflict between Interrupt Generation and Disabling
173
Figure 5.14 Conflict between Interrupt Generation and Disabling
173
Instructions for Disabling Interrupts
174
Interrupts During Execution of EEPMOV Instruction
174
Vector Address Switching
174
External Interrupt Pin in Software Standby Mode and Watch Mode
175
Noise Canceller Switching
175
IRQ Status Register (ISR)
175
Section 6 Bus Controller (BSC)
177
Features
177
Figure 6.1 Block Diagram of BSC
177
Register Descriptions
178
Bus Control Register (BCR)
178
Wait State Control Register (WSCR)
179
Bus Arbitration
180
Priority of Bus Masters
180
Bus Transfer Timing
180
Section 7 Data Transfer Controller (DTC)
183
Features
184
Figure 7.1 Block Diagram of DTC
184
Register Descriptions
185
DTC Mode Register a (MRA)
186
DTC Mode Register B (MRB)
187
DTC Source Address Register (SAR)
187
DTC Destination Address Register (DAR)
188
DTC Transfer Count Register a (CRA)
188
DTC Transfer Count Register B (CRB)
188
DTC Enable Registers (DTCER)
189
Table 7.1 Correspondence between Interrupt Sources and DTCER
189
DTC Vector Register (DTVECR)
190
Activation Sources
191
Figure 7.2 Block Diagram of DTC Activation Source Control
191
Location of Register Information and DTC Vector Table
192
Figure 7.3 DTC Register Information Location in Address Space
192
Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
193
Operation
195
Figure 7.4 DTC Operation Flowchart
195
Figure 7.5 Memory Mapping in Normal Mode
196
Normal Mode
196
Table 7.3 Register Functions in Normal Mode
196
Figure 7.6 Memory Mapping in Repeat Mode
197
Repeat Mode
197
Table 7.4 Register Functions in Repeat Mode
197
Block Transfer Mode
198
Figure 7.7 Memory Mapping in Block Transfer Mode
198
Table 7.5 Register Functions in Block Transfer Mode
198
Chain Transfer
199
Figure 7.8 Chain Transfer Operation
199
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
200
Interrupt Sources
200
Operation Timing
200
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
201
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
201
Number of DTC Execution States
202
Table 7.6 DTC Execution Status
202
Table 7.7 Number of States Required for each Execution Status
202
Procedures for Using DTC
203
Activation by Interrupt
203
Activation by Software
203
Examples of Use of the DTC
204
Normal Mode
204
Software Activation
205
Usage Notes
206
Module Stop Mode Setting
206
On-Chip RAM
206
DTCE Bit Setting
206
Setting Required on Entering Subactive Mode or Watch Mode
206
DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter
206
Section 8 I/O Ports
207
Table 8.1 Port Functions
207
Port 1
212
Port 1 Data Direction Register (P1DDR)
212
Port 1 Data Register (P1DR)
213
Port 1 Pull-Up MOS Control Register (P1PCR)
213
Pin Functions
214
Port 1 Input Pull-Up MOS
214
Table 8.2 Port 1 Input Pull-Up MOS States
214
Port 2
215
Port 2 Data Direction Register (P2DDR)
215
Port 2 Data Register (P2DR)
216
Port 2 Pull-Up MOS Control Register (P2PCR)
216
Pin Functions
217
Port 2 Input Pull-Up MOS
218
Table 8.3 Port 2 Input Pull-Up MOS States
218
Port 3
219
Port 3 Data Direction Register (P3DDR)
219
Port 3 Data Register (P3DR)
220
Port 3 Pull-Up MOS Control Register (P3PCR)
220
Pin Functions
221
Port 3 Input Pull-Up MOS
221
Table 8.4 Port 3 Input Pull-Up MOS States
221
Port 4
222
Port 4 Data Direction Register (P4DDR)
222
Port 4 Data Register (P4DR)
223
Pin Functions
223
Port 5
226
Port 5 Data Direction Register (P5DDR)
226
Port 5 Data Register (P5DR)
226
Pin Functions
227
Port 6
228
Port 6 Data Direction Register (P6DDR)
228
Port 6 Data Register (P6DR)
229
Pull-Up MOS Control Register (KMPCR)
229
Noise Canceller Enable Register (P6NCE)
230
Noise Canceller Mode Control Register (P6NCMC)
230
Noise Cancel Cycle Setting Register (P6NCCS)
231
Figure 8.1 Noise Cancel Circuit
232
Figure 8.2 Noise Cancel Operation
232
System Control Register 2 (SYSCR2)
233
Pin Functions
233
Port 6 Input Pull-Up MOS
236
Table 8.5 Port 6 Input Pull-Up MOS States
236
Port 7
237
Port 7 Input Data Register (P7PIN)
237
Pin Functions
238
Port 8
239
Port 8 Data Direction Register (P8DDR)
239
Port 8 Data Register (P8DR)
240
Pin Functions
241
Port 9
244
Port 9 Data Direction Register (P9DDR)
244
Port 9 Data Register (P9DR)
245
Port 9 Pull-Up MOS Control Register (P9PCR)
245
Pin Functions
246
Port 9 Input Pull-Up MOS
248
Table 8.6 Port 9 Input Pull-Up MOS States
248
Port a
249
Port a Data Direction Register (PADDR)
249
Port a Output Data Register (PAODR)
250
Port a Input Data Register (PAPIN)
250
Pin Functions
251
Port B
252
Port B Data Direction Register (PBDDR)
252
Port B Output Data Register (PBODR)
253
Port B Input Data Register (PBPIN)
253
Pin Functions
254
Port B Input Pull-Up MOS
256
Table 8.7 Port B Input Pull-Up MOS States
256
Port C
257
Port C Data Direction Register (PCDDR)
257
Port C Output Data Register (PCODR)
258
Port C Input Data Register (PCPIN)
258
Noise Canceller Enable Register (PCNCE)
259
Noise Canceller Mode Control Register (PCNCMC)
259
Noise Cancel Cycle Setting Register (PCNCCS)
260
Pin Functions
260
Port C Nch-OD Control Register (PCNOCR)
263
Pin Functions
263
8.12.10 Port C Input Pull-Up MOS
264
Table 8.8 Port C Input Pull-Up MOS States
264
Port D
265
Port D Data Direction Register (PDDDR)
265
Port D Output Data Register (PDODR)
266
Port D Input Data Register (PDPIN)
266
Pin Functions
267
Port D Nch-OD Control Register (PDNOCR)
271
Pin Functions
271
Port D Input Pull-Up MOS
272
Table 8.9 Port D Input Pull-Up MOS States
272
Port E
273
Port E Input Pull-Up MOS Control Register (PEPCR)
273
Port E Input Data Register (PEPIN)
273
Pin Functions
274
Port E Input Pull-Up MOS
274
Table 8.10 Port E Input Pull-Up MOS States
274
Port F
275
Port F Data Direction Register (PFDDR)
275
Port F Output Data Register (PFODR)
276
Port F Input Data Register (PFPIN)
276
Pin Functions
277
Port F Nch-OD Control Register (PFNOCR)
279
Pin Functions
279
Port F Input Pull-Up MOS
280
Table 8.11 Port F Input Pull-Up MOS States
280
Port G
281
Port G Data Direction Register
281
Port G Output Data Register
282
Port G Input Data Register
282
Noise Canceller Enable Register
283
Noise Canceller Mode Control Register
283
Noise Cancel Cycle Setting Register
284
Pin Functions
285
Port G Nch-OD Control Register
290
Pin Functions
290
Change of Peripheral Function Pins
291
Port Control Register 0 (PTCNT0)
291
Port Control Register 1 (PTCNT1)
292
Port Control Register 2 (PTCNT2)
293
Section 9 8-Bit PWM Timer (PWM)
295
Features
295
Figure 9.1 Block Diagram of PWM Timer
296
Input/Output Pins
297
Register Descriptions
297
Table 9.1 Pin Configuration
297
PWM Register Select (PWSL)
298
PWM Data Registers 15 to 8 (PWDR15 to PWDR8)
299
Table 9.2 Internal Clock Selection
299
Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency When Φ = 20 Mhz
299
PWM Data Polarity Register B (PWDPRB)
300
PWM Output Enable Register B (PWOERB)
300
Peripheral Clock Select Register (PCSR)
301
Operation
302
Table 9.4 Duty Cycle of Basic Pulse
302
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
303
Table 9.5 Position of Pulses Added to Basic Pulses
303
Diagram of PWM Used as D/A Converter
304
Figure 9.3 Example of PWM Setting
304
Figure 9.4 Example When PWM Is Used as D/A Converter
304
PWM Setting Example
304
Usage Notes
305
Module Stop Mode Setting
305
Section 10 14-Bit PWM Timer (PWMX)
307
Features
307
Figure 10.1 PWMX (D/A) Block Diagram
307
Input/Output Pins
308
Register Descriptions
308
Table 10.1 Pin Configuration
308
PWMX (D/A) Counter (DACNT)
309
PWMX (D/A) Data Registers a and B (DADRA and DADRB)
310
PWMX (D/A) Control Register (DACR)
312
Peripheral Clock Select Register (PCSR)
313
Table 10.2 Clock Select of PWMX
313
Bus Master Interface
314
Figure 10.2 (1) DACNT Access Operation (1) [CPU → DACNT(H'AA57) Writing]
315
Table 10.3 Reading/Writing to 16-Bit Registers
315
Figure 10.2 (2) DACNT Access Operation (2) [DACNT → CPU(H'AA57) Reading]
316
Operation
317
Figure 10.3 PWMX (D/A) Operation
317
Table 10.4 Settings and Operation (Examples When Φ = 20 Mhz)
318
Figure 10.4 Output Waveform (os = 0, DADR Corresponds to T L )
320
Figure 10.5 Output Waveform (os = 1, DADR Corresponds to T H )
321
Figure 10.6 D/A Data Register Configuration When CFS = 1
321
Figure 10.7 Output Waveform When DADR = H'0207 (os = 1)
322
Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
323
Usage Notes
324
Module Stop Mode Setting
324
Section 11 16-Bit Free-Running Timer (FRT)
325
Features
325
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
326
Input/Output Pins
327
Register Descriptions
327
Table 11.1 Pin Configuration
327
Free-Running Counter (FRC)
328
Input Capture Registers a to D (ICRA to ICRD)
328
Output Compare Registers a and B (OCRA and OCRB)
328
Output Compare Register DM (OCRDM)
329
Output Compare Registers AR and AF (OCRAR and OCRAF)
329
Timer Interrupt Enable Register (TIER)
330
Timer Control/Status Register (TCSR)
331
Timer Control Register (TCR)
334
Timer Output Compare Control Register (TOCR)
335
Operation
337
Pulse Output
337
Figure 11.2 Example of Pulse Output
337
Operation Timing
338
FRC Increment Timing
338
Figure 11.3 Increment Timing with Internal Clock Source
338
Figure 11.4 Increment Timing with External Clock Source
338
Output Compare Output Timing
339
FRC Clear Timing
339
Figure 11.5 Timing of Output Compare a Output
339
Figure 11.6 Clearing of FRC by Compare-Match a Signal
339
Input Capture Input Timing
340
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
340
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read)
340
Buffered Input Capture Input Timing
341
Figure 11.9 Buffered Input Capture Timing
341
Timing of Input Capture Flag (ICF) Setting
342
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
342
Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
342
Timing of Output Compare Flag (OCF) Setting
343
Timing of FRC Overflow Flag Setting
343
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
343
Automatic Addition Timing
344
Figure 11.13 Timing of Overflow Flag (OVF) Setting
344
Figure 11.14 OCRA Automatic Addition Timing
344
11.5.10 Mask Signal Generation Timing
345
Figure 11.15 Timing of Input Capture Mask Signal Setting
345
Figure 11.16 Timing of Input Capture Mask Signal Clearing
345
Interrupt Sources
346
Table 11.2 FRT Interrupt Sources
346
Usage Notes
347
Conflict between FRC Write and Clear
347
Figure 11.17 Conflict between FRC Write and Clear
347
Conflict between FRC Write and Increment
348
Figure 11.18 Conflict between FRC Write and Increment
348
Conflict between OCR Write and Compare-Match
349
Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used)
349
Switching of Internal Clock and FRC Operation
350
Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Used)
350
Table 11.3 Switching of Internal Clock and FRC Operation
351
Module Stop Mode Setting
352
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Renesas H8S/2100 Series Hardware Manual (1024 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 6.38 MB
Table of Contents
Table of Contents
9
Section 1 Overview
27
Features
27
Applications
27
Overview of Functions
28
List of Products
33
Block Diagram
34
Pin Descriptions
35
Pin Assignments
35
Pin Assignment in each Operating Mode
38
Pin Functions
45
Section 2 CPU
55
Features
55
Differences between H8S/2600 CPU and H8S/2000 CPU
56
Differences from H8/300 CPU
57
Differences from H8/300H CPU
57
CPU Operating Modes
58
Normal Mode
58
Advanced Mode
60
Address Space
62
Registers
63
General Registers
64
Program Counter (PC)
65
Extended Control Register (EXR)
65
Condition-Code Register (CCR)
66
Multiply-Accumulate Register (MAC)
67
Initial Values of CPU Registers
67
Data Formats
68
General Register Data Formats
68
Memory Data Formats
70
Instruction Set
71
Table of Instructions Classified by Function
72
Basic Instruction Formats
82
Addressing Modes and Effective Address Calculation
83
Register DirectRn
83
Register Indirect@Ern
83
Register Indirect with Displacement@(D:16, Ern) or @(D:32, Ern)
84
Register Indirect with Post-Increment or Pre-Decrement@Ern+ or @-Ern
84
Absolute Address@Aa:8, @Aa:16, @Aa:24, or @Aa:32
84
Immediate#XX:8, #XX:16, or #XX:32
85
Program-Counter Relative@(D:8, PC) or @(D:16, PC)
85
Memory Indirect@@Aa:8
86
Effective Address Calculation
87
Processing States
89
Usage Note
91
Notes on Using the Bit Operation Instruction
91
Section 3 MCU Operating Modes
93
Operating Mode Selection
93
Register Descriptions
94
Mode Control Register (MDCR)
94
System Control Register (SYSCR)
95
Serial Timer Control Register (STCR)
97
System Control Register 3 (SYSCR3)
99
Operating Mode Descriptions
99
Mode 2
99
Address Map
100
Section 4 Exception Handling
101
Exception Handling Types and Priority
101
Exception Sources and Exception Vector Table
102
Reset
105
Reset Exception Handling
105
Interrupts Immediately after Reset
106
On-Chip Peripheral Modules after Reset Is Cancelled
106
Interrupt Exception Handling
107
Trap Instruction Exception Handling
107
Exception Handling by Illegal Instruction
108
Stack Status after Exception Handling
109
Usage Note
110
Section 5 Interrupt Controller
111
Features
111
Input/Output Pins
113
Register Descriptions
114
Interrupt Control Registers a to D (ICRA to ICRD)
115
Address Break Control Register (ABRKCR)
117
Break Address Registers a to C (BARA to BARC)
118
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
119
IRQ Enable Registers (IER16, IER)
122
IRQ Status Registers (ISR16, ISR)
123
Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR)
125
IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR)
129
Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER)
130
Interrupt Sources
131
External Interrupt Sources
131
Internal Interrupt Sources
134
Interrupt Exception Handling Vector Tables
134
Interrupt Control Modes and Interrupt Operation
143
Interrupt Control Mode 0
145
Interrupt Control Mode 1
147
Interrupt Exception Handling Sequence
150
Interrupt Response Times
151
Address Breaks
152
Features
152
Block Diagram
152
Operation
153
Usage Notes
153
Usage Notes
155
Conflict between Interrupt Generation and Disabling
155
Instructions for Disabling Interrupts
156
Interrupts During Execution of EEPMOV Instruction
156
Vector Address Switching
156
External Interrupt Pin in Software Standby Mode and Watch Mode
157
Noise Canceller Switching
157
IRQ Status Register (ISR)
157
Section 6 Bus Controller (BSC)
159
Register Descriptions
159
Bus Control Register (BCR)
159
Wait State Control Register (WSCR)
160
Section 7 I/O Ports
161
Register Descriptions
169
Data Direction Register (Pnddr) (N = 1 to 6, 8, 9, a to D, and F to J)
170
Data Register (Pndr) (N = 1 to 6, 8, and 9)
171
Input Data Register (Pnpin) (N = 1 to 9 and a to J)
171
Pull-Up MOS Control Register (Pnpcr) (N = 1 to 3, 9, B to D, F, H, and J) Pull-Up MOS Control Register (KMPCR) (Port 6)
172
Output Data Register (Pnodr) (N = a to D and F to J)
175
Noise Canceler Enable Register (Pnnce) (N = 6, C, and G)
175
Noise Canceler Decision Control Register (Pnncmc) (N = 6, C, and G)
176
Noise Cancel Cycle Setting Register (Pnnccs) (N = 6, C, and G)
176
Port Nch-OD Control Register (Pnnocr) (N = C, D, and F to J)
178
Pin Functions
179
Output Buffer Control
180
Port 1
180
Port 2
180
Port 3
181
Port 4
181
Port 5
185
Port 6
187
Port 7
188
Port 8
189
Port 9
192
Port a
194
Port B
195
Port C
199
Port D
203
Port E
203
Port F
204
Port G
207
Port H
211
Port I
213
Port J
213
Change of Peripheral Function Pins
220
Port Control Register 0 (PTCNT0)
220
Port Control Register 1 (PTCNT1)
221
Port Control Register 2 (PTCNT2)
222
Section 8 8-Bit PWM Timer (PWMU)
223
Features
223
Input/Output Pins
225
Register Descriptions
226
PWM Control Register a (PWMCONA)
228
PWM Control Register B (PWMCONB)
228
PWM Control Register C (PWMCONC)
231
PWM Control Register D (PWMCOND)
232
PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5)
233
PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5)
235
Operation
236
Single-Pulse Mode (8 Bits, 16 Bits)
236
Pulse Division Mode
240
Usage Note
243
Setting Module Stop Mode
243
Note on Using 16-Bit Single-Pulse PWM Timer
243
Section 9 14-Bit PWM Timer (PWMX)
245
Features
245
Input/Output Pins
246
Register Descriptions
246
PWMX (D/A) Counter (DACNT)
247
PWMX (D/A) Data Registers a and B (DADRA and DADRB)
248
PWMX (D/A) Control Register (DACR)
250
Peripheral Clock Select Register (PCSR)
251
Bus Master Interface
252
Operation
255
Usage Notes
262
Module Stop Mode Setting
262
Section 10 16-Bit Timer Pulse Unit (TPU)
263
Features
263
Input/Output Pins
267
Register Descriptions
268
Timer Control Register (TCR)
269
Timer Mode Register (TMDR)
273
Timer I/O Control Register (TIOR)
275
Timer Interrupt Enable Register (TIER)
284
Timer Status Register (TSR)
286
Timer Counter (TCNT)
289
Timer General Register (TGR)
289
Timer Start Register (TSTR)
289
Timer Synchro Register (TSYR)
290
Interface to Bus Master
291
16-Bit Registers
291
Operation
293
Basic Functions
293
Synchronous Operation
299
Buffer Operation
301
PWM Modes
305
Phase Counting Mode
309
Interrupts
314
Interrupt Source and Priority
314
A/D Converter Activation
315
Operation Timing
316
Input/Output Timing
316
Interrupt Signal Timing
320
Usage Notes
323
Input Clock Restrictions
323
Caution on Period Setting
323
Conflict between TCNT Write and Clear Operations
324
Conflict between TCNT Write and Increment Operations
324
Conflict between TGR Write and Compare Match
325
Conflict between Buffer Register Write and Compare Match
325
Conflict between TGR Read and Input Capture
326
Conflict between TGR Write and Input Capture
327
Conflict between Buffer Register Write and Input Capture
327
10.8.10 Conflict between Overflow/Underflow and Counter Clearing
328
10.8.11 Conflict between TCNT Write and Overflow/Underflow
329
10.8.12 Multiplexing of I/O Pins
329
10.8.13 Module Stop Mode Setting
329
Renesas H8S/2100 Series Hardware Manual (984 pages)
6-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 6.16 MB
Table of Contents
Table of Contents
9
Section 1 Overview
27
Features
27
Applications
27
Overview of Functions
28
List of Products
33
Block Diagram
34
Pin Descriptions
35
Pin Assignments
35
Pin Assignment in each Operating Mode
38
Pin Functions
45
Section 2 CPU
55
Features
55
Differences between H8S/2600 CPU and H8S/2000 CPU
56
CPU Operating Modes
57
Address Space
59
Registers
60
General Registers
61
Program Counter (PC)
62
Extended Control Register (EXR)
62
Condition-Code Register (CCR)
63
Initial Values of CPU Registers
64
Data Formats
65
General Register Data Formats
65
Memory Data Formats
67
Instruction Set
68
Table of Instructions Classified by Function
69
Basic Instruction Formats
79
Addressing Modes and Effective Address Calculation
80
Register DirectRn
80
Register Indirect@Ern
80
Register Indirect with Displacement@(D:16, Ern) or @(D:32, Ern)
81
Register Indirect with Post-Increment or Pre-Decrement@Ern+ or @-Ern
81
Absolute Address@Aa:8, @Aa:16, @Aa:24, or @Aa:32
81
Immediate#XX:8, #XX:16, or #XX:32
82
Program-Counter Relative@(D:8, PC) or @(D:16, PC)
82
Memory Indirect@@Aa:8
83
Effective Address Calculation
84
Processing States
86
Usage Note
88
TAS Instruction
88
STM/LDM Instruction
88
Notes on Using the Bit Operation Instruction
88
EEPMOV Instruction
89
Section 3 MCU Operating Modes
91
Operating Mode Selection
91
Register Descriptions
92
Mode Control Register (MDCR)
92
System Control Register (SYSCR)
93
Serial Timer Control Register (STCR)
95
System Control Register 3 (SYSCR3)
97
Port Control Register 2 (PTCNT2)
98
Operating Mode Descriptions
99
Mode 2
99
Address Map
99
Section 4 Resets
101
Types of Resets
101
Input/Output Pin
102
Register Descriptions
103
Reset Status Register (RSTSR)
103
System Control Register (SYSCR)
104
Timer Control/Status Register (TCSR)
106
Pin Reset
109
Power-On Reset
110
Watchdog Timer Reset
111
Determination of Reset Generation Source
111
Section 5 Exception Handling
113
Exception Handling Types and Priority
113
Exception Sources and Exception Vector Table
114
Reset
117
Reset Exception Handling
117
Interrupts Immediately after Reset
118
On-Chip Peripheral Modules after Reset Is Cancelled
118
Interrupt Exception Handling
119
Trap Instruction Exception Handling
119
Stack Status after Exception Handling
120
Usage Note
121
Section 6 Interrupt Controller
123
Features
123
Input/Output Pins
125
Register Descriptions
126
Interrupt Control Registers a to D (ICRA to ICRD)
127
Address Break Control Register (ABRKCR)
129
Break Address Registers a to C (BARA to BARC)
130
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
131
IRQ Enable Registers (IER16, IER)
134
IRQ Status Registers (ISR16, ISR)
135
IRQ Sense Port Select Registers 16 (ISSR16) IRQ Sense Port Select Registers (ISSR)
137
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMRB) Wake-Up Event Interrupt Mask Registers (WUEMRA, WUEMRB)
138
Wake-Up Sense Control Register (WUESCRA, WUESCRB) Wake-Up Input Interrupt Status Register (WUESRA, WUESRB) Wake-Up Enable Register (WUEER)
142
Interrupt Sources
145
External Interrupt Sources
145
Internal Interrupt Sources
148
Interrupt Exception Handling Vector Tables
149
Interrupt Control Modes and Interrupt Operation
157
Interrupt Control Mode 0
159
Interrupt Control Mode 1
161
Interrupt Exception Handling Sequence
164
Interrupt Response Times
165
Address Breaks
166
Features
166
Block Diagram
166
Operation
167
Usage Notes
167
Usage Notes
169
Conflict between Interrupt Generation and Disabling
169
Instructions for Disabling Interrupts
170
Interrupts During Execution of EEPMOV Instruction
170
Vector Address Switching
170
External Interrupt Pin in Software Standby Mode and Watch Mode
171
Noise Canceler Switching
171
IRQ Status Register (ISR)
171
Section 7 Bus Controller (BSC)
173
Register Descriptions
173
Bus Control Register (BCR)
173
Wait State Control Register (WSCR)
174
Section 8 I/O Ports
175
Register Descriptions
182
Data Direction Register (Pnddr) (N = 1 to 6, 8, 9, a to D, and F to H)
183
Data Register (Pndr) (N = 1 to 6, 8, and 9)
184
Input Data Register (Pnpin) (N = 1 to 9 and a to J)
184
Pull-Up MOS Control Register (Pnpcr) (N = 1 to 3, 6, 9, B to D, F, and H)
185
Output Data Register (Pnodr) (N = a to D and F to H)
186
Noise Canceler Enable Register (Pnnce) (N = 4, 6, C, and G)
187
Noise Canceler Decision Control Register (Pnncmc) (N = 4, 6, C, and G)
187
Noise Cancel Cycle Setting Register (Pnnccs) (N = 4, 6, C, and G)
188
Port Nch-OD Control Register (Pnnocr) (N = C, D, F, G, and H)
189
MOS State of Output Buffer
190
Pin Functions
191
Port 1
191
Port 2
191
Port 3
192
Port 4
193
Port 5
196
Port 6
197
Port 7
198
Port 8
198
Port 9
201
Port a
202
Port B
203
Port C
206
Port D
210
Port E
211
Port F
212
Port G
214
Port H
218
Change of Peripheral Function Pins
219
Port Control Register 0 (PTCNT0)
219
Port Control Register 1 (PTCNT1)
220
Port Control Register 2 (PTCNT2)
221
Section 9 8-Bit PWM Timer (PWMU)
223
Features
223
Input/Output Pins
225
Register Descriptions
226
PWM Clock Control Register (PWMCKCR)
228
PWM Output Control Register B (PWMOUTCR)
228
PWM Mode Control Register C (PWMMDCR)
231
PWM Phase Control Register (PWMPCR)
232
PWM Prescaler Latch Register (PRELAT)
233
PWM Duty Setting Latch Register (REGLAT)
234
PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5)
235
PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5)
238
Operation
240
Single-Pulse Mode (8 Bits, 12 Bits, and 16 Bits)
240
Pulse Division Mode
244
Usage Note
247
Setting Module Stop Mode
247
Note on Using 16-Bit/12-Bit Single-Pulse PWM Timer
247
Section 10 16-Bit Timer Pulse Unit (TPU)
249
Features
249
Input/Output Pins
253
Register Descriptions
254
Timer Control Register (TCR)
255
Timer Mode Register (TMDR)
259
Timer I/O Control Register (TIOR)
261
Timer Interrupt Enable Register (TIER)
270
Timer Status Register (TSR)
272
Timer Counter (TCNT)
275
Timer General Register (TGR)
275
Timer Start Register (TSTR)
275
Timer Synchro Register (TSYR)
276
Interface to Bus Master
277
16-Bit Registers
277
Operation
279
Basic Functions
279
Synchronous Operation
285
Buffer Operation
287
PWM Modes
291
Phase Counting Mode
295
Interrupts
300
Interrupt Source and Priority
300
A/D Converter Activation
301
Operation Timing
302
Input/Output Timing
302
Interrupt Signal Timing
306
Usage Notes
309
Input Clock Restrictions
309
Caution on Period Setting
309
Conflict between TCNT Write and Clear Operations
310
Conflict between TCNT Write and Increment Operations
310
Conflict between TGR Write and Compare Match
311
Conflict between Buffer Register Write and Compare Match
311
Conflict between TGR Read and Input Capture
312
Conflict between TGR Write and Input Capture
312
Conflict between Buffer Register Write and Input Capture
313
10.8.10 Conflict between Overflow/Underflow and Counter Clearing
314
10.8.11 Conflict between TCNT Write and Overflow/Underflow
314
10.8.12 Multiplexing of I/O Pins
315
10.8.13 Module Stop Mode Setting
315
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