Figure 16.21 Example Of Slave Receive Mode Operation Timing (1) (Mls = Ackb = 0, Hnds = 0); Figure 16.22 Example Of Slave Receive Mode Operation Timing (2) (Mls = Ackb = 0, Hnds = 0) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
Start condition issuance
SCL
(master output)
SDA
(master output)
SDA
(slave output)
IRIC
ICDRF
ICDRS
ICDRR
User processing
Figure 16.21 Example of Slave Receive Mode Operation Timing (1)
SCL
(master output)
8 9 1
SDA
Bit 0 Bit 7
(master output)
Data n-2
[11]
SDA
(slave output)
A
IRIC
ICDRF
ICDRS
Data n-2
ICDRR
User processing
[13] IRIC clear
Figure 16.22 Example of Slave Receive Mode Operation Timing (2)
Rev. 3.00 Jul. 14, 2005 Page 558 of 986
REJ09B0098-0300
1 2 3
Bit 7 Bit 6 Bit 5
Slave address
Address+R/W
(MLS = ACKB = 0, HNDS = 0)
2 3 4 5 6 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data n-1
Data n-2
[9] Wait for one frame
(MLS = ACKB = 0, HNDS = 0)
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
8 9 1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
A
Data n-1
[13] IRIC clear
[10] ICDR read
[10] ICDR read
(Data n-1)
(Data n-2)
[9] Set ACKB = 1
8 9 1 2
Bit 0 Bit 7 Bit 6
[6]
R/W Data 1
A
Data 1
[7]
Address+R/W
[8] IRIC clear
[10] ICDR read
Stop condition detection
5 6 7 8 9
[11]
Data n
A
Data n-1
[13] IRIC clear
[14] ICDR read
(Data n)
3 4
Bit 5 Bit 4
[11]
Data n
Data n
[15] IRIC clear