Section 19 A/D Converter
AVCC
AVref
10-bit D/A
AVSS
AN0
AN1
AN2
AN3
AN4
Sample-and-hold
AN5
circuit
AN6
AN7
ADTRG
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Rev. 3.00 Jul. 14, 2005 Page 718 of 986
REJ09B0098-0300
Module data bus
A
A
D
D
D
D
R
R
A
B
+
Comparator
Figure 19.1 Block Diagram of A/D Converter
A
A
A
A
D
D
D
D
D
D
C
C
R
R
S
R
C
D
R
Control circuit
Conversion start trigger from TPU or 8-bit timer
Internal data bus
φ/8
φ/16
ADI interrupt signal