Figure 16.18 Example Of Slave Receive Mode Operation Timing (1) (Mls = 0, Hnds= 1) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
Start condition generation
SCL
(Pin waveform)
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
IRIC
ICDRF
ICDRS
ICDRR
User processing
[2] ICDR read
Figure 16.18 Example of Slave Receive Mode Operation Timing (1)
Rev. 3.00 Jul. 14, 2005 Page 554 of 986
REJ09B0098-0300
1 2 3 4 5
1 2 3 4 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Slave address
Undefined value
(MLS = 0, HNDS= 1)
[7] SCL is fixed low until ICDR is read
6 7 8 9
6 7 8 9
Bit 2 Bit 1 Bit 0
R/W
[6]
A
Interrupt
request
occurrence
Address
+R/W
Address
[8] IRIC clear
1 2
1 2
Bit 7 Bit 6
Data 1
+R/W
[10] ICDR read (dummy read)