16.4.10 Initialization Of Internal State - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)

16.4.10 Initialization of Internal State

The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch
Register (DDCSWR).
(1) Scope of Initialization
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags)
• Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, and ICSR
• The value of the ICMR bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
(2) Notes on Initialization
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not
retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR.
• Similarly, when clearing is required again, all the bits must be written to simultaneously in
accordance with the setting.
Rev. 3.00 Jul. 14, 2005 Page 568 of 986
REJ09B0098-0300