Kclki And Kdi Read Timing; Figure 17.9 Kclki And Kdi Read Timing - Renesas H8S Series Hardware Manual

Section 17 Keyboard Buffer Control Unit (KBU)
17.4.4

KCLKI and KDI Read Timing

Figure 17.9 shows the KCLKI and KDI read timing.
φ*
Internal read
signal
KCLK, KD
(pin state)
KCLKI, KDI
(register)
Internal data bus
(read data)
The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
Note:*
mode is active mode.
Rev. 3.00 Jul. 14, 2005 Page 600 of 986
REJ09B0098-0300
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Figure 17.9 KCLKI and KDI Read Timing

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