Table 16.7 Operation By Using Dtc - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)

Table 16.7 Operation by Using DTC

Master Transmit
Item Mode
Slave address +
Transmission by
R/W bit DTC (ICDR write)
transmission/
reception
Dummy data read 
2
I C data Transmission by
transmission/ DTC (ICDR write)
reception

Dummy data
(H'FF) write
Last frame Not required
processing
Transfer request 1st time: Clearing
processing after by CPU
last frame 2nd time: Stop
processing condition issue by
completed CPU
Set the number of Transmission: The
frames of DTC number of actual
data + 1 (+ 1 =
transfer data
slave address +
R/W bit)
Rev. 3.00 Jul. 14, 2005 Page 566 of 986
REJ09B0098-0300
Master Receive Slave Transmit
Mode Mode
Transmission by Reception by CPU
CPU (ICDR write) (ICDR read)

Processing by
CPU (ICDR read)
Transmission by Transmission by
DTC (ICDR read) DTC (ICDR write)

Processing by
DTC (ICDR write)
Reception by CPU Not required
(ICDR read)
Not required Dummy data
(H'FF)
Stop condition
detection and
automatic clear
during
transmission
Reception: The Transmission: The
number of actual number of actual
data + 1 (+ 1 =
data
dummy data
(H'FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)

Reception by DTC
(ICDR read)

Reception by CPU
(ICDR read)
Not required
Reception: The
number of actual
data