Conflict Between Tcnt Write And Count-Up; Figure 13.14 Conflict Between Tcnt Write And Count-Up - Renesas H8S Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.9.2

Conflict between TCNT Write and Count-Up

If a count-up occurs during the T
counter write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 13.14 Conflict between TCNT Write and Count-Up

Rev. 3.00 Jul. 14, 2005 Page 408 of 986
REJ09B0098-0300
state of a TCNT write cycle as shown in figure 13.14, the
2
TCNT write cycle by CPU
T 1
TCNT address
N
T 2
M
Counter write data