Hardware Standby Mode; Figure 24.4 Hardware Standby Mode Timing - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Section 24 Power-Down Modes

Hardware Standby Mode

The CPU makes a transition to hardware standby mode from any mode when the STBY pin is

In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is

supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the STBY pin low. Do not change the state of the mode pins (MD2, MD1, and MD0)

while this LSI is in hardware standby mode.

Hardware standby mode is cleared by the STBY pin input or the RES pin input.

When the STBY pin is driven high while the RES pin is low, the clock pulse generator starts

oscillation. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the

RES pin is subsequently driven high after the clock oscillation stabilization time has elapsed, reset

exception handling starts.

Figure 24.4 shows an example of hardware standby mode timing.

Rev. 3.00 Jul. 14, 2005 Page 874 of 986

REJ09B0098-0300

stabilization

H8s/2100 series H8s/2114r R4f2114r