Figure 21.6 System Configuration In Boot Mode; Figure 21.7 Automatic-Bit-Rate Adjustment Operation Of Sci - Renesas H8S Series Hardware Manual

Host
Boot
programming
tool and
program data
(1) SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI
communication data (H'00) which is transmitted consecutively from the host. The SCI
transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate
of transmission by the host by means of the measured low period and transmits the bit adjustment
end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign
(H'00) has been received normally and then transmits 1 byte of H'55 to this LSI. When reception
has not been executed normally, boot mode is initiated again (reset) and the operation described
above must be performed. The bit rates of the host and this LSI do not match due to the bit rate of
transmission by the host and the system clock frequency of this LSI. To operate the SCI normally,
the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 21.6. Boot mode must be initiated in the range of this
system clock.
Start
bit

Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI

Control command and
program data
Reply response

Figure 21.6 System Configuration in Boot Mode

D0 D1 D2
Measure low period (9 bits) (data is H'00)
Section 21 Flash Memory (0.18-µm F-ZTAT Version)
Analysis
execution
software
(on-chip)
RxD1
On-chip SCI_1
TxD1
D3 D4 D5 D6
Rev. 3.00 Jul. 14, 2005 Page 765 of 986
This LSI
Flash
memory
On-chip
RAM
Stop bit
D7
High period of
at least 1 bit
REJ09B0098-0300