Renesas H8S Series Hardware Manual page 181

(2) DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC is a bus master with lower priority than the LPC, and if a bus request is received from
the LPC, the bus arbiter transfers the bus to the LPC.
• LPC bus transfer timing
The bus is transferred at a break between bus cycles.
If a bus cycle is executed in discrete operations, as in the case of a longword-size access, the
bus is not transferred between the component operations. Similarly, in case of a 32-bit access
by the DTC, the bus is not transferred between the component operations for each longword.
(3) LPC
The LPC has the highest bus master priority. The LPC sends the bus arbiter a request for the bus
when an activation request is generated. The LPC does not release the bus until it completes
reading/writing the on-chip memory. For details, see section 18, LPC Interface (LPC).
Section 6 Bus Controller (BSC)
Rev. 3.00 Jul. 14, 2005 Page 133 of 986
REJ09B0098-0300