Register Addresses (Address Order) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Register Addresses (Address Order)

The data bus width indicates the numbers of bits by which the register is accessed.

The number of access states indicates the number of states based on the specified reference clock.

Timer control register_1

Timer mode register_1

Timer I/O control register_1

Timer interrupt enable register_1

Timer Status register_1

Timer counter_1

Timer general register A_1

Timer general register B_1

LPC channel 4 address register H

LPC channel 4 address register L

Input data register 4

Output data register 4

Status register 4

Host interface control register 4

SERIRQ control register 2

RAM buffer address register

Erase block register

LMC status register 1

LMC status register 2

LMC control register 1

LMC control register 2

On-chip RAM protect control register MPCR

Host base address register 1H

Host base address register 1L

Host base address register 2H

Host base address register 2L

Abbreviation

Section 25 List of Registers

Rev. 3.00 Jul. 14, 2005 Page 883 of 986

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r