Timer Control/Status Register (Tcsr) - Renesas H8S Series Hardware Manual

Bit Bit Name Initial Value
2 OCIBE 0
1 OVIE 0

0 1
11.3.7

Timer Control/Status Register (TCSR)

TCSR is used for counter clear selection and control of interrupt request signals.
Bit Bit Name Initial Value
7 ICFA 0
R/W Description
R/W Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
R/W Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
R Reserved
This bit is always read as 1 and cannot be modified.
R/W Description
R/(W)* Input Capture Flag A
This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture
signal. When BUFEA = 1, ICFA indicates that the old
ICRA value has been moved into ICRC and the new
FRC value has been transferred to ICRA.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRA
[Clearing condition]
Read ICFA when ICFA = 1, then write 0 to ICFA
Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Jul. 14, 2005 Page 283 of 986
REJ09B0098-0300