Interval Timer Mode; Figure 14.2 Watchdog Timer Mode (Rst/Nmi = 1) Operation; Figure 14.3 Interval Timer Mode Operation - Renesas H8S Series Hardware Manual

H'FF
H'00
Internal reset signal
WT/IT : Timer mode select bit
TME : Timer enable bit
: Overflow flag
OVF
Note * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.

Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation

14.4.2

Interval Timer Mode

When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at
intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is
requested at the same time the OVF flag of TCSR is set to 1. The timing is shown figure 14.4.
TCNT value
H'FF
H'00
WT/IT = 0
TME = 1
WOVI : Interval timer interrupt request occurrence
TCNT value
WT/IT = 1 Write H'00 to
TME = 1 TCNT
Overflow
WOVI

Figure 14.3 Interval Timer Mode Operation

Overflow
OVF = 1* WT/IT = 1
TME = 1
518 System clocks
Overflow Overflow
WOVI WOVI
Rev. 3.00 Jul. 14, 2005 Page 421 of 986
Section 14 Watchdog Timer (WDT)
Time
Write H'00 to
TCNT
Overflow
Time
WOVI
REJ09B0098-0300