Section 10 14-Bit PWM Timer (PWMX)
(a) Read upper byte
CPU
[H'AA]
Upper byte
(b) Read lower byte
CPU
[H'57]
Lower byte
Figure 10.2 (2) DACNT Access Operation (2) [DACNT → CPU(H'AA57) Reading]
Rev. 3.00 Jul. 14, 2005 Page 268 of 986
REJ09B0098-0300
Bus interface
Bus interface
Module data bus
TEMP
[H'AA]
DACNTH
DACNTL
[
]
[
]
Module data bus
TEMP
[H'AA]
DACNTH
DACNTL
[H'AA]
[H'57]