Host Interface Select Register (Hisel) - Renesas H8S Series Hardware Manual

18.3.13 Host Interface Select Register (HISEL)

HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt
request signal of each frame.
Initial
Bit Bit Name Value
7 SELSTR3 0
6 SELIRQ11 0
5 SELIRQ10 0
4 SELIRQ9 0
3 SELIRQ6 0
2 SELSMI 0
1 SELIRQ12 1
0 SELIRQ1 1
R/W
Slave Host Description

R/W Status Register 3 Selection
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. For
details of STR3, see section 18.3.9, Status Registers
1 to 4 (STR1 to STR4).
0: Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are readable/writable bits
which user can use as necessary

R/W SERIRQ Output Select

R/W Select the pin output status of SERIRQ.

R/W 0: [When host interrupt request is cleared]

R/W
SERIRQ pin output is in the Hi-Z state

[When host interrupt request is set]
R/W

SERIRQ pin output is low
R/W
1: [When host interrupt request is cleared]

R/W
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 653 of 986
REJ09B0098-0300