Renesas Single-Chip Microcomputer SH7203 Manuals

Manuals and User Guides for Renesas Single-Chip Microcomputer SH7203. We have 2 Renesas Single-Chip Microcomputer SH7203 manuals available for free PDF download: Hardware Manual, Application Note

Renesas Single-Chip Microcomputer SH7203 Hardware Manual (1622 pages)

Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family / SH7200 Series

Brand: Renesas | Category: Computer Hardware | Size: 10.61 MB

General Precautions on Handling of Product
4
Preface
6
Contents
8
Table of Contents
9
Section 1 Overview

31
- SH7203 Features
  31
- Product Lineup
  39
- Block Diagram
  40
- Pin Arrangement
  41
- Pin Functions
  42
Section 2 CPU

53
- Register Configuration
  53
  - General Registers
    53
  - Index
    53
  - Control Registers
    54
  - System Registers
    56
  - Register Banks
    57
  - Initial Values of Registers
    57
- Data Formats
  58
  - Data Format in Registers
    58
  - Data Formats in Memory
    58
  - Immediate Data Format
    59
- Instruction Features
  60
  - RISC-Type Instruction Set
    60
  - Addressing Modes
    64
  - Instruction Format
    69
- Instruction Set
  73
- Processing States
  96
Section 3 Floating-Point Unit (FPU)

99
- Features
  99
- Data Formats
  100
  - Floating-Point Format
    100
  - Non-Numbers (Nan)
    103
  - Denormalized Numbers
    104
- Register Descriptions
  105
- Rounding
  108
- Floating-Point Exceptions
  109
  - FPU Exception Sources
    109
  - FPU Exception Handling
    109
Section 4 Clock Pulse Generator (CPG)

111
- Features
  111
- Input/Output Pins
  115
- Clock Operating Modes
  116
- Register Descriptions
  121
  - Frequency Control Register (FRQCR)
    121
- Changing the Frequency
  124
  - Changing the Multiplication Rate
    124
  - Changing the Division Ratio
    125
- Notes on Board Design
  126
Section 5 Exception Handling

129
- Overview
  129
- Resets
  135
  - Input/Output Pins
    135
  - Types of Reset
    135
  - Power-On Reset
    136
  - Manual Reset
    138
- Address Errors
  139
  - Address Error Sources
    139
  - Address Error Exception Handling
    140
- Register Bank Errors
  141
  - Register Bank Error Sources
    141
  - Register Bank Error Exception Handling
    141
- Interrupts
  142
  - Interrupt Sources
    142
  - Interrupt Priority Level
    143
  - Interrupt Exception Handling
    144
- Exceptions Triggered by Instructions
  145
  - Types of Exceptions Triggered by Instructions
    145
  - Trap Instructions
    146
  - Slot Illegal Instructions
    146
  - General Illegal Instructions
    147
  - Integer Division Instructions
    147
  - Floating Point Operation Instructions
    148
- When Exception Sources Are Not Accepted
  149
- Stack Status after Exception Handling Ends
  150
- Usage Notes
  152
Section 6 Interrupt Controller (INTC)

153
- Features
  153
- Input/Output Pins
  155
- Register Descriptions
  156
- Interrupt Sources
  169
  - NMI Interrupt
    169
  - User Break Interrupt
    169
  - H-UDI Interrupt
    169
  - IRQ Interrupts
    169
  - PINT Interrupts
    170
  - On-Chip Peripheral Module Interrupts
    171
- Interrupt Exception Handling Vector Table and Priority
  172
- Operation
  182
  - Interrupt Operation Sequence
    182
  - Stack after Interrupt Exception Handling
    185
- Interrupt Response Time
  186
- Register Banks
  192
- Data Transfer with Interrupt Request Signals
  197
  - Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating
    198
  - Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt
    198
- Usage Note
  199
  - Timing to Clear an Interrupt Source
    199
Section 7 User Break Controller (UBC)

201
- Features
  201
- Input/Output Pin
  203
- Register Descriptions
  204
  - Break Address Register (BAR)
    205
  - Break Address Mask Register (BAMR)
    206
  - Break Data Register (BDR)
    207
  - Break Data Mask Register (BDMR)
    208
  - Break Bus Cycle Register (BBR)
    209
  - Break Control Register (BRCR)
    211
- Operation
  215
  - Flow of the User Break Operation
    215
  - Break on Instruction Fetch Cycle
    216
  - Break on Data Access Cycle
    217
  - Value of Saved Program Counter
    218
  - Usage Examples
    219
- Usage Notes
  222
Section 8 Cache

223
- Features
  223
  - Cache Structure
    223
- Register Descriptions
  226
  - Cache Control Register 1 (CCR1)
    226
  - Cache Control Register 2 (CCR2)
    228
- Operation
  232
  - Searching Cache
    232
  - Read Access
    234
  - Prefetch Operation (Only for Operand Cache)
    234
  - Write Operation (Only for Operand Cache)
    235
  - Write-Back Buffer (Only for Operand Cache)
    235
  - Coherency of Cache and External Memory
    237
- Memory-Mapped Cache
  238
  - Address Array
    238
  - Data Array
    239
  - Usage Examples
    241
  - Notes
    241
Section 9 Bus State Controller (BSC)

243
- Features
  243
- Input/Output Pins
  246
- Area Overview
  248
  - Address Map
    248
  - Data Bus Width and Pin Function Setting in each Area
    249
- Register Descriptions
  250
- Operation
  305
  - Endian/Access Size and Data Alignment
    305
  - Normal Space Interface
    312
  - Access Wait Control
    317
  - Csn Assert Period Expansion
    319
  - MPX-I/O Interface
    320
  - SDRAM Interface
    324
  - Burst ROM (Clocked Asynchronous) Interface
    368
  - SRAM Interface with Byte Selection
    370
  - PCMCIA Interface
    375
  - Burst MPX-I/O Interface
    382
  - Burst ROM (Clocked Synchronous) Interface
    387
  - Wait between Access Cycles
    388
  - Bus Arbitration
    395
  - Others
    397
Section 10 Direct Memory Access Controller (DMAC)

401
- Features
  401
- Input/Output Pins
  404
- Register Descriptions
  405
- Operation
  430
  - Transfer Flow
    430
  - DMA Transfer Requests
    432
  - Channel Priority
    437
  - DMA Transfer Types
    440
  - Normal Mode
    444
  - Number of Bus Cycles and DREQ Pin Sampling Timing
    449
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

453
Section 12 Compare Match Timer (CMT)

669
- Features
  669
- Register Descriptions
  670
- Operation
  675
  - Interval Count Operation
    675
  - CMCNT Count Timing
    675
- Interrupts
  676
- Usage Notes
  678
Section 13 Watchdog Timer (WDT)

681
- Features
  681
- Input/Output Pin
  683
- Register Descriptions
  684
- WDT Usage
  690
  - Canceling Software Standby Mode
    690
  - Changing the Frequency
    690
  - Using Watchdog Timer Mode
    691
  - Using Interval Timer Mode
    693
- Usage Notes
  694
  - Timer Variation
    694
  - Prohibition against Setting H'FF to WTCNT
    694
  - System Reset by WDTOVF Signal
    694
  - Manual Reset in Watchdog Timer Mode
    695
Section 14 Realtime Clock (RTC)

697
- Features
  697
- Input/Output Pin
  699
- Register Descriptions
  700
  - 64-Hz Counter (R64CNT)
    701
  - Second Counter (RSECCNT)
    702
  - Minute Counter (RMINCNT)
    703
  - Hour Counter (RHRCNT)
    704
  - Day of Week Counter (RWKCNT)
    705
  - Date Counter (RDAYCNT)
    706
  - Month Counter (RMONCNT)
    707
  - Year Counter (RYRCNT)
    708
  - Second Alarm Register (RSECAR)
    709
  - Minute Alarm Register (RMINAR)
    710
  - Hour Alarm Register (RHRAR)
    711
  - Day of Week Alarm Register (RWKAR)
    712
  - Date Alarm Register (RDAYAR)
    713
  - Month Alarm Register (RMONAR)
    714
  - Year Alarm Register (RYRAR)
    715
  - RTC Control Register 1 (RCR1)
    716
  - RTC Control Register 2 (RCR2)
    718
  - RTC Control Register 3 (RCR3)
    720
- Operation
  721
  - Initial Settings of Registers after Power-On
    721
  - Setting Time
    721
  - Reading Time
    722
  - Alarm Function
    723
- Usage Notes
  724
Section 15 Serial Communication Interface with FIFO (SCIF)

727
- Features
  727
- Input/Output Pins
  730
- Register Descriptions
  731
  - Receive Shift Register (SCRSR)
    733
  - Receive FIFO Data Register (SCFRDR)
    733
  - Transmit Shift Register (SCTSR)
    734
  - Transmit FIFO Data Register (SCFTDR)
    734
  - Serial Mode Register (SCSMR)
    735
  - Serial Control Register (SCSCR)
    738
  - Serial Status Register (SCFSR)
    742
  - Bit Rate Register (SCBRR)
    750
  - FIFO Control Register (SCFCR)
    760
  - FIFO Data Count Set Register (SCFDR)
    763
  - Serial Port Register (SCSPTR)
    764
  - Line Status Register (SCLSR)
    767
  - Serial Extension Mode Register (SCEMR)
    768
- Operation
  769
  - Overview
    769
  - Operation in Asynchronous Mode
    772
  - Operation in Clock Synchronous Mode
    783
- SCIF Interrupts
  791
- Usage Notes
  792
Section 16 Synchronous Serial Communication Unit (SSU)

797
- Features
  797
- Input/Output Pins
  799
- Register Descriptions
  800
  - SS Control Register H (SSCRH)
    801
  - SS Control Register L (SSCRL)
    803
  - SS Mode Register (SSMR)
    804
  - SS Enable Register (SSER)
    805
  - SS Status Register (SSSR)
    806
  - SS Control Register 2 (SSCR2)
    809
  - SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
    810
  - SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
    811
  - SS Shift Register (SSTRSR)
    812
- Operation
  813
- SSU Interrupt Sources and DMAC
  835
- Usage Note
  836
  - Module Standby Mode Setting
    836
Section 17 I C Bus Interface 3 (IIC3)

837
- Features
  837
- Input/Output Pins
  839
- Register Descriptions
  840
  - C Bus Control Register 1 (ICCR1)
    841
  - C Bus Control Register 2 (ICCR2)
    844
  - C Bus Mode Register (ICMR)
    846
  - C Bus Interrupt Enable Register (ICIER)
    848
  - C Bus Status Register (ICSR)
    850
  - Slave Address Register (SAR)
    853
  - C Bus Transmit Data Register (ICDRT)
    853
  - C Bus Receive Data Register (ICDRR)
    854
  - C Bus Shift Register (ICDRS)
    854
  - NF2CYC Register (NF2CYC)
    855
- Operation
  856
  - C Bus Format
    856
  - Master Transmit Operation
    857
  - Master Receive Operation
    859
  - Slave Transmit Operation
    861
  - Slave Receive Operation
    864
  - Clocked Synchronous Serial Format
    865
  - Noise Filter
    869
  - Example of Use
    870
- Interrupt Requests
  874
- Bit Synchronous Circuit
  875
Section 18 Serial Sound Interface (SSI)

877
- Features
  877
- Input/Output Pins
  880
- Register Description
  881
  - Control Register (SSICR)
    882
  - Status Register (SSISR)
    888
  - Transmit Data Register (SSITDR)
    893
  - Receive Data Register (SSIRDR)
    893
- Operation Description
  894
  - Bus Format
    894
  - Non-Compressed Modes
    895
  - Operation Modes
    905
  - Transmit Operation
    906
  - Receive Operation
    909
  - Temporary Stop and Restart Procedures in Transmit Mode
    912
  - Serial Bit Clock Control
    913
- Usage Notes
  914
  - Limitations from Overflow During Receive DMA Operation
    914
  - Note on Using Oversampling Clock
    914
Section 19 Controller Area Network (RCAN-TL1)

915
- Summary
  915
  - Overview
    915
  - Scope
    915
  - Audience
    915
  - References
    915
  - Features
    916
- Architecture
  917
- Programming Model - Overview
  920
  - Memory Map
    920
  - Mailbox Structure
    922
  - Master Mode
    924
  - RCAN-TL1 Control Registers
    939
  - RCAN-TL1 Mailbox Registers
    960
  - Timer Registers
    975
- Application Note
  989
  - Test Mode Settings
    989
  - Configuration of RCAN-TL1
    991
  - Message Transmission Sequence
    996
  - Message Receive Sequence
    1010
  - Reconfiguration of Mailbox
    1012
- Interrupt Sources
  1014
- DMAC Interface
  1015
- CAN Bus Interface
  1016
- Setting I/O Ports for RCAN-TL1
  1017
- Usage Notes
  1019
  - Notes on Port Setting for Multiple Channels Used as Single Channel
    1019
Section 20 A/D Converter (ADC)

1021
- Features
  1021
- Input/Output Pins
  1023
- Register Descriptions
  1024
  - A/D Data Registers a to H (ADDRA to ADDRH)
    1025
  - A/D Control/Status Register (ADCSR)
    1026
- Operation
  1030
  - Single Mode
    1030
  - Multi Mode
    1033
  - Scan Mode
    1035
  - A/D Converter Activation by External Trigger or MTU2
    1038
  - Input Sampling and A/D Conversion Time
    1038
  - External Trigger Input Timing
    1040
- Interrupt Sources and DMAC Transfer Request
  1041
- Definitions of A/D Conversion Accuracy
  1042
- Usage Notes
  1043
  - Module Standby Mode Setting
    1043
  - Setting Analog Input Voltage
    1043
  - Notes on Board Design
    1043
  - Processing of Analog Input Pins
    1044
  - Permissible Signal Source Impedance
    1045
  - Influences on Absolute Precision
    1046
Section 21 D/A Converter (DAC)

1047
- Features
  1047
- Input/Output Pins
  1048
- Register Descriptions
  1049
  - D/A Data Registers 0 and 1 (DADR0 and DADR1)
    1049
  - D/A Control Register (DACR)
    1050
- Operation
  1052
- Usage Notes
  1053
  - Module Standby Mode Setting
    1053
  - D/A Output Hold Function in Software Standby Mode
    1053
  - Setting Analog Input Voltage
    1053
Section 22 AND/NAND Flash Memory Controller (FLCTL)

1055
- Features
  1055
- Input/Output Pins
  1059
- Register Descriptions
  1060
  - Common Control Register (FLCMNCR)
    1061
  - Command Control Register (FLCMDCR)
    1064
  - Command Code Register (FLCMCDR)
    1067
  - Address Register (FLADR)
    1068
  - Address Register 2 (FLADR2)
    1070
  - Data Counter Register (FLDTCNTR)
    1071
  - Data Register (FLDATAR)
    1072
  - Interrupt DMA Control Register (FLINTDMACR)
    1073
  - Ready Busy Timeout Setting Register (FLBSYTMR)
    1078
  - Ready Busy Timeout Counter (FLBSYCNT)
    1079
  - Data FIFO Register (FLDTFIFO)
    1080
  - Control Code FIFO Register (FLECFIFO)
    1081
  - Transfer Control Register (FLTRCR)
    1083
- Operation
  1084
  - Access Sequence
    1084
  - Operating Modes
    1085
  - Register Setting Procedure
    1086
  - Command Access Mode
    1087
  - Sector Access Mode
    1092
  - ECC Error Correction
    1094
  - Status Read
    1095
- Interrupt Sources
  1097
- DMA Transfer Specifications
  1098
Section 23 USB 2.0 Host/Function Module (USB)

1099
- Features
  1099
- Input / Output Pins
  1101
- Register Description
  1103
- Operation
  1168
  - System Control and Oscillation Control
    1168
  - Interrupt Functions
    1170
  - Pipe Control
    1188
  - Buffer Memory
    1195
  - Control Transfers (DCP)
    1209
  - Bulk Transfers (PIPE1 to PIPE5)
    1212
  - Interrupt Transfers (PIPE6 and PIPE7)
    1214
  - Isochronous Transfers (PIPE1 and PIPE2)
    1215
  - SOF Interpolation Function
    1222
  - 23.4.10 Pipe Schedule
    1224
Section 24 LCD Controller (LCDC)

1227
Section 25 Pin Function Controller (PFC)

1295
- Features
  1301
- Register Descriptions
  1302
- Switching Pin Function of Port a
  1357
- Usage Notes
  1358
Section 26 I/O Ports

1359
- Features
  1359
- Port a
  1360
  - Register Descriptions
    1360
  - Port a Data Register L (PADRL)
    1360
- Port B
  1362
  - Register Descriptions
    1362
  - Port B Data Register L (PBDRL)
    1363
  - Port B Port Register L (PBPRL)
    1365
- Port C
  1366
  - Register Descriptions
    1366
  - Port C Data Register L (PCDRL)
    1367
  - Port C Port Register L (PCPRL)
    1369
- Port D
  1370
  - Register Descriptions
    1370
  - Port D Data Registers L (PDDRL)
    1371
  - Port D Port Registers L (PDPRL)
    1373
- Port E
  1374
  - Register Descriptions
    1374
  - Port E Data Registers L (PEDRL)
    1375
  - Port E Port Registers L (PEPRL)
    1377
- Port F
  1378
- Usage Notes
  1385
Section 27 On-Chip RAM

1387
- Features
  1387
- Usage Notes
  1389
  - Page Conflict
    1389
  - RAME and RAMWE Bits
    1389
  - Areas Where Placing Instructions Is Prohibited
    1390
Section 28 Power-Down Modes

1391
- Features
  1391
  - Power-Down Modes
    1391
- Register Descriptions
  1394
  - Standby Control Register (STBCR)
    1395
  - Standby Control Register 2 (STBCR2)
    1396
  - Standby Control Register 3 (STBCR3)
    1397
  - Standby Control Register 4 (STBCR4)
    1399
  - Standby Control Register 5 (STBCR5)
    1401
  - Standby Control Register 6 (STBCR6)
    1403
  - System Control Register 1 (SYSCR1)
    1405
  - System Control Register 2 (SYSCR2)
    1407
  - System Control Register 3 (SYSCR3)
    1408
  - Deep Standby Control Register (DSCTR)
    1410
  - Deep Standby Control Register 2 (DSCTR2)
    1412
  - Deep Standby Cancel Source Select Register (DSSSR)
    1413
  - Deep Standby Cancel Source Flag Register (DSFR)
    1415
- Operation
  1417
  - Sleep Mode
    1417
  - Software Standby Mode
    1418
  - Software Standby Mode Application Example
    1420
  - Deep Standby Mode
    1421
  - Module Standby Function
    1427
- Usage Notes
  1428
Section 29 User Debugging Interface (H-UDI)

1429
- Features
  1429
- Input/Output Pins
  1430
- Register Descriptions
  1431
  - Bypass Register (SDBPR)
    1431
  - Instruction Register (SDIR)
    1431
- Operation
  1433
  - TAP Controller
    1433
  - Reset Configuration
    1434
  - TDO Output Timing
    1434
  - H-UDI Reset
    1435
  - H-UDI Interrupt
    1435
- Usage Notes
  1436
Section 30 List of Registers

1437
- Register Addresses
  1438
  - (By Functional Module, in Order of the Corresponding Section Numbers)
    1438
- Register Bits
  1461
- Register States in each Operating Mode
  1509
Section 31 Electrical Characteristics

1513
- Absolute Maximum Ratings
  1513
- Power-On/Power-Off Sequence
  1514
- DC Characteristics
  1515
- AC Characteristics
  1523
  - Clock Timing
    1524
  - Control Signal Timing
    1528
  - Bus Timing
    1531
  - UBC Trigger Timing
    1566
  - DMAC Module Timing
    1567
  - MTU2 Module Timing
    1568
  - Watchdog Timer Timing
    1569
  - SCIF Module Timing
    1570
  - Serial Communication Unit (SSU) Timing
    1571
  - 31.4.10 IIC3 Module Timing
    1574
  - 31.4.11 SSI Module Timing
    1576
  - RCAN-TL1 Module Timing
    1578
  - A/D Trigger Input Timing
    1579
  - 31.4.14 FLCTL Module Timing
    1580
  - 31.4.15 USB Transceiver Timing
    1588
  - LCDC Module Timing
    1590
  - I/O Port Timing
    1592
  - H-UDI Related Pin Timing
    1593
  - 31.4.19 AC Characteristics Measurement Conditions
    1595
- A/D Converter Characteristics
  1596
- D/A Converter Characteristics
  1597
Appendix

1599
- Pin States
  1599
- Package Dimensions
  1605
Index

1607

Renesas Single-Chip Microcomputer SH7203 Application Note (19 pages)

Data Transfer to On-chip Peripheral Modules with DMAC

Brand: Renesas | Category: Computer Hardware | Size: 0.13 MB

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Renesas Single-Chip Microcomputer SH7203 Manuals

Renesas Single-Chip Microcomputer SH7203 Hardware Manual (1622 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 Floating-Point Unit (FPU)

Section 4 Clock Pulse Generator (CPG)

Section 5 Exception Handling

Section 6 Interrupt Controller (INTC)

Section 7 User Break Controller (UBC)

Section 8 Cache

Section 9 Bus State Controller (BSC)

Section 10 Direct Memory Access Controller (DMAC)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Section 12 Compare Match Timer (CMT)

Section 13 Watchdog Timer (WDT)

Section 14 Realtime Clock (RTC)

Section 15 Serial Communication Interface with FIFO (SCIF)

Section 16 Synchronous Serial Communication Unit (SSU)

Section 17 I C Bus Interface 3 (IIC3)

Section 18 Serial Sound Interface (SSI)

Section 19 Controller Area Network (RCAN-TL1)

Section 20 A/D Converter (ADC)

Section 21 D/A Converter (DAC)

Section 22 AND/NAND Flash Memory Controller (FLCTL)

Section 23 USB 2.0 Host/Function Module (USB)

Section 24 LCD Controller (LCDC)

Section 25 Pin Function Controller (PFC)

Section 26 I/O Ports

Section 27 On-Chip RAM

Section 28 Power-Down Modes

Section 29 User Debugging Interface (H-UDI)

Section 30 List of Registers

Section 31 Electrical Characteristics

Appendix

Index

Renesas Single-Chip Microcomputer SH7203 Application Note (19 pages)

Table of Contents

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