Interrupt Sources; Table 16.8 Iic Interrupt Sources - Renesas H8S Series Hardware Manual

• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
4. Initialize (re-set) the IIC registers.
16.5

Interrupt Sources

The IIC has interrupt source IICI. Table 16.8 shows the interrupt sources and priority. Individual
interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the
interrupt controller independently.
The IIC interrupts are used as on-chip DTC activation sources.

Table 16.8 IIC Interrupt Sources

Channel Name
0 IICI0
1 IICI1
Enable Bit Interrupt Source
2
IEIC I C bus interface interrupt
request
2
IEIC I C bus interface interrupt
request
2
Section 16 I C Bus Interface (IIC)
Interrupt Flag Priority
IRIC
IRIC
Rev. 3.00 Jul. 14, 2005 Page 569 of 986
REJ09B0098-0300
High
Low