Figure 23.6 Timing Of External Clock Output Stabilization Delay Time; Table 23.4 External Clock Output Stabilization Delay Time - Renesas H8S Series Hardware Manual

Table 23.4 External Clock Output Stabilization Delay Time

Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V
Item
External clock output stabilization delay
time
includes a RES pulse width (t
Note: t
*
DEXT
3.0 V
V
CC
V
STBY
IH
EXTAL
φ
(Internal and external)
RES
Note: The external clock output stabilization delay time (t

Figure 23.6 Timing of External Clock Output Stabilization Delay Time

Symbol Min
t * 500
DEXT
).
RESW
t *
DEXT
) includes a RES pulse width (t
DEXT
Section 23 Clock Pulse Generator
Max Unit
 µs
).
RESW
Rev. 3.00 Jul. 14, 2005 Page 853 of 986
REJ09B0098-0300
Remarks
Figure 23.6