Figure 22.3 Reset Signal Circuit Without Reset Signal Interference - Renesas H8S Series Hardware Manual

Board edge pin
System reset
ETRST

Figure 22.3 Reset Signal Circuit without Reset Signal Interference

3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode,
IDCODE mode will be entered.
4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see
section 26, Electrical Characteristics.
5. Data input/output in serial data transfer starts from the LSB. Figure 22.4 and 22.5 shows
examples of serial data input/output.
6. When data that exceeds the number of bits of the register connected between the ETDI and
ETDO pins is serially transferred, the serial data that exceeds the number of register bits and
output from the ETDO pin is the same as that input from the ETDI pin.
7. If the JTAG serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer
should then be retried, regardless of the transfer operation.
8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be
detected at the corresponding input scan register. In this case, the corresponding enable scan
register should be cleared to 0.
9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its
corresponding output scan register is 1, 0 can be detected at the corresponding enable scan
register.
Power-on
reset circuit
Section 22 Boundary Scan (JTAG)
This LSI
RES
ETRST
Rev. 3.00 Jul. 14, 2005 Page 847 of 986
REJ09B0098-0300