Usage Notes; Module Stop Mode Setting; On-Chip Ram; Dtce Bit Setting - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Section 7 Data Transfer Controller (DTC)

Usage Notes

DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the

initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop

mode is set. Note that when the DTC is being activated, module stop mode can not be specified.

For details, see section 24, Power-Down Modes.

MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,

the RAME bit in SYSCR should not be cleared to 0.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and

writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by

masking all interrupts and writing data after executing a dummy read on the relevant register.

Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm

that is set to 1 before making a transition to subactive mode or watch mode.

Interrupt sources of the SCI, IIC, LPC, or A/D converter which activate the DTC are cleared when

DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit

Rev. 3.00 Jul. 14, 2005 Page 158 of 986

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r