Subclock Input Circuit; Figure 23.7 Subclock Input From Excl Pin And Exexcl Pin; Table 23.5 Subclock Input Conditions - Renesas H8S Series Hardware Manual

23.5

Subclock Input Circuit

The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the
subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin.
Figure 23.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin.
When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the
pin to 0. The EXCL pin is specified as an input pin by clearing the EXCLS bit in PTCNT0 to 0.
The ExEXCL pin is specified as an input pin by setting the EXCLS bit in PTCNT0 to 1. The
subclock input is enabled by setting the EXCLE bit in LPWRCR to 1.

Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin

Subclock input conditions are shown in table 23.5. When the subclock is not used, subclock input
should not be enabled.

Table 23.5 Subclock Input Conditions

Item
Subclock input pulse width
low level
Subclock input pulse width
high level
Subclock input rising time
Subclock input falling time
EXCLS
(PTCNT0)
P96/EXCL
P50/ExEXCL
Symbol
Min

t
EXCLL

t
EXCLH

t
EXCLr

t
EXCLf
EXCLE
(LPWRCR)
Subclock
VCC = 3.0 to 3.6 V
Typ Max

15.26

15.26

10

10
Rev. 3.00 Jul. 14, 2005 Page 855 of 986
Section 23 Clock Pulse Generator
Unit Test Conditions
µs
Figure 23.8
µs
ns
ns
REJ09B0098-0300