Conflict Between Tgr Write And Input Capture; Figure 12.50 Conflict Between Tgr Write And Input Capture - Renesas H8S Series Hardware Manual

12.8.8

Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to TGR is not performed. Figure 12.50 shows the timing
in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 12.50 Conflict between TGR Write and Input Capture

Section 12 16-Bit Timer Pulse Unit (TPU)
state of a TGR write cycle, the input capture
2
TGR write cycle
T1 T2
TGR address
M
M
Rev. 3.00 Jul. 14, 2005 Page 373 of 986
REJ09B0098-0300