Conflict Between Buffer Register Write And Input Capture; Figure 12.51 Conflict Between Buffer Register Write And Input Capture - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.9

Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to the buffer register is not performed. Figure 12.51
shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register

Figure 12.51 Conflict between Buffer Register Write and Input Capture

Rev. 3.00 Jul. 14, 2005 Page 374 of 986
REJ09B0098-0300
state of a buffer register write cycle, the buffer
2
Buffer register write cycle
T1 T2
Buffer register
address
N
M N
M