Table 16.4 Flags And Transfer States (Master Mode) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
Tables 16.4 and 16.5 show the relationship between the flags and the transfer states.

Table 16.4 Flags and Transfer States (Master Mode)

MST TRS BBSY ESTP
1 1 0 0
1 1 1↑ 0
1 — 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
Rev. 3.00 Jul. 14, 2005 Page 522 of 986
REJ09B0098-0300
STOP IRTR AASX AL
0 0 0↓ 0
0 1↑ 0 0
0 — 0 0
0 — 0 0
0 1↑ 0 0
0 — 0 0
0 — 0 0
0 — 0 0
0 1↑ 0 0
0 1↑ 0 0
0 — 0 0
0 — 0 0
0 — 0 0
0 1↑ 0 0
AAS ADZ ACKB ICDRF ICDRE State
0↓ 0↓ 0 —
0 0 0 —
0 0 — —
0 0 1↑ —
0 0 0 —
0 0 0 —
0 0 0 —
0 0 0 —
0 0 0 —
0 0 — 1↑
0 0 — 0↓
0 0 — 1
0 0 — 0↓
0 0 — 1↑
0 Idle state (flag
clearing
required)
1↑ Start condition
detected
— Wait state
— Transmission
end (ACKE=1
and ACKB=1)
1↑ Transmission
end with
ICDRE=0
0↓ ICDR write with
the above state
1 Transmission
end with
ICDRE=1
0↓ ICDR write with
the above state
or after start
condition
detected
1↑ Automatic data
transfer from
ICDRT to ICDRS
with the above
state
— Reception end
with ICDRF=0
— ICDR read with
the above state
— Reception end
with ICDRF=1
— ICDR read with
the above state
— Automatic data
transfer from
ICDRS to
ICDRR with the
above state