C Bus Status Register (Icsr) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
2
16.3.6 I

C Bus Status Register (ICSR)

ICSR consists of status flags. Also see tables 16.4 and 16.5.
Bit Bit Name Initial Value R/W
7 ESTP 0
6 STOP 0
5 IRTR 0
Rev. 3.00 Jul. 14, 2005 Page 526 of 986
REJ09B0098-0300
Description
R/(W)* Error Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag in ICCR is cleared to 0
R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag is cleared to 0
2
R/(W)* I C Bus Interface Continuous Transfer Interrupt Request
Flag
Indicates that the I
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception. When the IRTR flag is set to 1, the
IRIC flag is also set to 1 at the same time.
[Setting conditions]
2
I C bus format slave mode:
•
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format mode
2
with I C bus format:
•
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
•
When 0 is written after reading IRTR = 1
•
When the IRIC flag is cleared to 0 while ICE is 1
2
C bus format slave mode.
2
C bus format slave mode.
2
C bus interface has issued an interrupt