Conflict Between Overflow/Underflow And Counter Clearing; Conflict Between Tcnt Write And Overflow/Underflow; Figure 9.54 Conflict Between Overflow And Counter Clearing; Figure 9.55 Conflict Between Tcnt Write And Overflow - Renesas H8SX/1500 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.11

Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag

Figure 9.54 Conflict between Overflow and Counter Clearing

9.9.12

Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.55 shows the operation timing when there is conflict between TCNT write and overflow.
Pφ
Address
Write
TCNT
TCFV flag

Figure 9.55 Conflict between TCNT Write and Overflow

Rev. 3.00 Mar. 14, 2006 Page 342 of 804
REJ09B0104-0300
H'FFFF
Disabled
TGR write cycle
T1 T2
TCNT address
H'FFFF
H'0000
TCNT write data
M