Bus Arbitration; Priority Of Bus Masters; Bus Transfer Timing - Renesas H8S Series Hardware Manual

Section 6 Bus Controller (BSC)
6.3

Bus Arbitration

The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters –
CPU, DTC, and LPC – which perform read/write operations when they have possession of the
bus.
6.3.1

Priority of Bus Masters

Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters' bus request signals, and sends a bus request acknowledge signal to the bus master making
the request at the designated timing. If there are bus requests from more than one bus master, the
bus request acknowledge signal is sent to the one with the highest priority. When a bus master
receives the bus request acknowledge signal, it takes possession of the bus until that signal is
canceled. The priority order of the bus masters is as follows:
(High) LPC > DTC > CPU (Low)
6.3.2

Bus Transfer Timing

When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. Each bus master can relinquish the bus at the timings given below.
(1) CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or LPC,
the bus arbiter transfers the bus to the DTC or LPC.
• DTC and LPC bus transfer timing
 The bus is transferred at a break between bus cycles.
However, if a bus cycle is executed in discrete operations, as in the case of a longword-size
access, the bus is not transferred between the component operations. For details, see section
2.7, Bus States During Instruction Execution, in the H8S/2600 Series, H8S/2000 Series
Programming Manual.
 If the CPU is in sleep mode, the bus is transferred immediately.
Rev. 3.00 Jul. 14, 2005 Page 132 of 986
REJ09B0098-0300