Figure 8.1 Noise Cancel Circuit; Figure 8.2 Noise Cancel Operation - Renesas H8S Series Hardware Manual

Section 8 I/O Ports
φ/2, φ/32, φ/8192, φ/16384, φ/32768,
φ/65536, φ/131072, φ/262144
Sampling clock selection
t
Pin
Latch
input
Sampling clock
P6n Input
1 expected
P6n Input
0 expected
P6n Input
(n = 7 to 0)
Rev. 3.00 Jul. 14, 2005 Page 184 of 986
REJ09B0098-0300
Latch Latch
t

Figure 8.1 Noise Cancel Circuit

Figure 8.2 Noise Cancel Operation

Latch
Port data
register
Interrupt input
Key board input