Preface - Renesas H8S Series Hardware Manual

This H8S/2114R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU
with Renesas Technology's original architecture as its core, and the peripheral functions required
to configure a system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit
free running timer (FRT), a 16-bit timer pulse unit (TPU), 8-bit timers (TMR), watchdog timer
(WDT), serial communication interface (SCI), I
keyboard buffer control units (KBU), an A/D converter, and I/O ports as on-chip peripheral
modules required for system configuration.
A data transfer controller (DTC) and LPC interface (LPC) are included as bus masters.
A flash memory (F-ZTAT
connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This
improves the instruction fetch and process speeds.
TM
Note: * F-ZTAT
Target Users: This manual was written for users who use the H8S/2114R in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logic circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2114R Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions and electrical
characteristics.
Rev. 3.00 Jul. 14, 2005 Page vi of xlviii
TM
*) is available for this LSI's 1 Mbyte ROM. The CPU and ROM are
is a trademark of Renesas Technology. Corp.

Preface

2
C bus interface (IIC), a LPC interface (LPC), a