Renesas H8S Series Hardware Manual page 20
16-bit single-chip microcomputer
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Also See for H8S Series:
- Hardware manual (1047 pages) ,
- User manual (38 pages) ,
- User manual (21 pages)
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12.8.3 Conflict between TCNT Write and Clear Operations........................................... 369
12.8.4 Conflict between TCNT Write and Increment Operations ................................... 369
12.8.5 Conflict between TGR Write and Compare Match............................................... 370
12.8.6 Conflict between Buffer Register Write and Compare Match.............................. 371
12.8.7 Conflict between TGR Read and Input Capture ................................................... 372
12.8.8 Conflict between TGR Write and Input Capture .................................................. 373
12.8.9 Conflict between Buffer Register Write and Input Capture.................................. 374
12.8.10 Conflict between Overflow/Underflow and Counter Clearing ............................. 375
12.8.11 Conflict between TCNT Write and Overflow/Underflow .................................... 376
12.8.12 Multiplexing of I/O Pins ....................................................................................... 376
12.8.13 Module Stop Mode Setting ................................................................................... 376
Section 13 8-Bit Timer (TMR).......................................................................... 377
13.1 Features.............................................................................................................................. 377
13.2 Input/Output Pins............................................................................................................... 381
13.3 Register Descriptions......................................................................................................... 382
13.3.1 Timer Counter (TCNT)......................................................................................... 383
13.3.2 Time Constant Register A (TCORA) ................................................................... 383
13.3.3 Time Constant Register B (TCORB).................................................................... 384
13.3.4 Timer Control Register (TCR).............................................................................. 384
13.3.5 Timer Control/Status Register (TCSR)................................................................. 389
13.3.6 Time Constant Register C (TCORC).................................................................... 394
13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 394
13.3.8 Timer Input Select Register (TISR)...................................................................... 395
13.3.9 Timer Connection Register I (TCONRI) .............................................................. 395
13.3.10 Timer Connection Register S (TCONRS) ............................................................ 396
13.3.11 Timer XY Control Register (TCRXY) ................................................................. 396
13.4 Operation ........................................................................................................................... 397
13.4.1 Pulse Output ......................................................................................................... 397
13.5 Operation Timing............................................................................................................... 398
13.5.1 TCNT Count Timing ............................................................................................ 398
13.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 399
13.5.3 Timing of Timer Output at Compare-Match......................................................... 399
13.5.4 Timing of Counter Clear at Compare-Match........................................................ 400
13.5.5 TCNT External Reset Timing............................................................................... 400
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 401
13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 402
13.6.1 16-Bit Count Mode ............................................................................................... 402
13.6.2 Compare-Match Count Mode ............................................................................... 402
13.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 403
Rev. 3.00 Jul. 14, 2005 Page xx of xlviii
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