Input/Output Pins; Register Descriptions; Table 21.2 Pin Configuration - Renesas H8S Series Hardware Manual

Section 21 Flash Memory (0.18-µm F-ZTAT Version)
5. Consecutive execution of programming/erasing
When the 128-byte programming or one-block erasure does not end the processing, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program remains in the on-chip RAM even after the processing
ends, download and initialization are not required when the same processing is executed
consecutively.
21.2

Input/Output Pins

Flash memory is controlled by the pins listed in table 21.2.

Table 21.2 Pin Configuration

Pin Name Input/Output
RES
Input
FWE Input
MD2 Input
MD1 Input
MD0 Input
TxD1 Output
RxD1 Input
21.3

Register Descriptions

The registers/parameters that control flash memory are shown below. To read from or write to
these registers/parameters, the FLSHE bit in STCR must be set to 1. For details on STCR, see
section 3.2.3, Serial Timer Control Register (STCR).
• Flash code control status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass/fail result (DPFR)
• Flash pass/fail result (FPFR)
Rev. 3.00 Jul. 14, 2005 Page 744 of 986
REJ09B0098-0300
Function
Reset
Flash memory programming/erasing enable pin
Sets operating mode of this LSI
Sets operating mode of this LSI
Sets operating mode of this LSI
Serial transmit data output (used in boot mode)
Serial receive data input (used in boot mode)