Serirq Control Register 0 (Sirqcr0) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
Bit Bit Name Initial Value Slave Host Description
0 OBF4 0
Note: * Only 0 can be written to clear the flag.

18.3.10 SERIRQ Control Register 0 (SIRQCR0)

SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Bit Bit Name Initial Value Slave Host Description
7 Q/C 0
Rev. 3.00 Jul. 14, 2005 Page 640 of 986
REJ09B0098-0300
R/W
R/(W)* R Output Buffer Full
0: [Clearing conditions]
•
When the host reads ODR4 in I/O read cycle
•
When the slave writes 0 to the OBF3 bit
1: [Setting condition]
•
When the slave writes to ODR4
R/W

R Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end of
an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
•
LPC hardware reset, LPC software reset
•
Specification by SERIRQ transfer cycle stop
frame
1: Quiet mode
[Setting condition]
•
Specification by SERIRQ transfer cycle stop
frame.