Input Capture Input Timing; Figure 11.7 Input Capture Input Signal Timing (Usual Case); Figure 11.8 Input Capture Input Signal Timing (When Icra To Icrd Is Read) - Renesas H8S Series Hardware Manual

Section 11 16-Bit Free-Running Timer (FRT)
11.5.4

Input Capture Input Timing

The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal

Figure 11.7 Input Capture Input Signal Timing (Usual Case)

If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (φ). Figure 11.8 shows the timing for this case.
φ
Input capture
input pin
Input capture signal

Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)

Rev. 3.00 Jul. 14, 2005 Page 292 of 986
REJ09B0098-0300
Read cycle of ICRA to ICRD
T 1 T 2