Renesas H8S Series Hardware Manual page 45

Section 10 14-Bit PWM Timer (PWMX)
Table 10.1 Pin Configuration.................................................................................................. 260
Table 10.2 Clock Select of PWMX ........................................................................................ 265
Table 10.3 Reading/Writing to 16-bit Registers ..................................................................... 267
Settings and Operation (Examples when φ = 20 MHz)......................................... 270
Table 10.4
Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 275
Section 11 16-Bit Free-Running Timer (FRT)
Table 11.1 Pin Configuration.................................................................................................. 279
Table 11.2 FRT Interrupt Sources .......................................................................................... 298
Table 11.3 Switching of Internal Clock and FRC Operation .................................................. 303
Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.1 TPU Functions ...................................................................................................... 307
Table 12.2 Pin Configuration.................................................................................................. 309
Table 12.3 CCLR2 to CCLR0 (channel 0) ............................................................................. 312
Table 12.4 CCLR2 to CCLR0 (channels 1 and 2) .................................................................. 312
Table 12.5 TPSC2 to TPSC0 (channel 0) ............................................................................... 313
Table 12.6 TPSC2 to TPSC0 (channel 1) ............................................................................... 313
Table 12.7 TPSC2 to TPSC0 (channel 2) ............................................................................... 314
Table 12.8 MD3 to MD0 ........................................................................................................ 316
Table 12.9 TIORH_0 (channel 0) ........................................................................................... 318
Table 12.10 TIORH_0 (channel 0) ....................................................................................... 319
Table 12.11 TIORL_0 (channel 0)........................................................................................ 320
Table 12.12 TIORL_0 (channel 0)........................................................................................ 321
Table 12.13 TIOR_1 (channel 1) .......................................................................................... 322
Table 12.14 TIOR_1 (channel 1) .......................................................................................... 323
Table 12.15 TIOR_2 (channel 2) .......................................................................................... 324
Table 12.16 TIOR_2 (channel 2) .......................................................................................... 325
Table 12.17 Register Combinations in Buffer Operation ..................................................... 343
Table 12.18 PWM Output Registers and Output Pins .......................................................... 348
Table 12.19 Phase Counting Mode Clock Input Pins ........................................................... 352
Table 12.20 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 353
Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 354
Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 355
Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 356
Table 12.24 TPU Interrupts .................................................................................................. 358
Section 13 8-Bit Timer (TMR)
Table 13.1 Pin Configuration.................................................................................................. 381
Table 13.2 Clock Input to TCNT and Count Condition (1) .................................................... 386
Rev. 3.00 Jul. 14, 2005 Page xlv of xlviii