Table 18.8 Lpc Memory Cycle - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)
address, or an on-chip memory is written after receiving an address and data. So, if a transfer cycle
forced termination (abort) after receiving an address and data, an on-chip memory may be
accessed.

Table 18.8 LPC Memory Cycle

LPC Memory Read Cycle
State
Count Contents
1 Start
2 Cycle type/direction
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Address 5
8 Address 6
9 Address 7
10 Address 8
11 Turnaround (recovery) Host
12 Turnaround
13 Wait*
14 Synchronization
15 Data 1
16 Data 2
17 Turnaround (recovery) Slave
18 Turnaround
Note: * The number of wait states differs depending on the length of the time to turn the bus
control over and the system clock frequency.
Rev. 3.00 Jul. 14, 2005 Page 690 of 986
REJ09B0098-0300
Drive Value
Source (3 to 0)
Host 0000
Host 0000
Host Bits 31 to 28
Host Bits 27 to 24
Host Bits 23 to 20
Host Bits 19 to 16
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
1111
None ZZZZ
Slave 0101/0110
Slave 0000
Slave Bits 3 to 0
Slave Bits 7 to 4
1111
None ZZZZ
LPC Memory Write Cycle
Contents
Start
Cycle type/direction
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Data 1
Data 2
Turnaround (recovery) Host
Turnaround
Synchronization
Turnaround (recovery) Slave
Turnaround

Drive Value
Source (3 to 0)
Host 0000
Host 0010
Host Bits 31 to 28
Host Bits 27 to 24
Host Bits 23 to 20
Host Bits 19 to 16
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host Bits 3 to 0
Host Bits 7 to 4
1111
None ZZZZ
Slave 0000
1111
None ZZZZ
 