Renesas H8S Series Hardware Manual page 47

Section 17 Keyboard Buffer Control Unit (KBU)
Table 17.1 Pin Configuration.................................................................................................. 584
Section 18 LPC Interface (LPC)
Table 18.1 Pin Configuration.................................................................................................. 616
Table 18.2 LPC I/O Cycle ...................................................................................................... 678
Table 18.3 GA20 (P81) Setting/Clearing Timing ................................................................... 680
Table 18.4 Fast Gate A20 Output Signals............................................................................... 682
Table 18.5 Scope of LPC Interface Pin Shutdown ................................................................. 684
Table 18.6 Scope of Initialization in Each LPC interface Mode............................................. 685
Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration .................................... 688
Table 18.8 LPC Memory Cycle .............................................................................................. 690
Table 18.9 FW Memory Cycle (Byte Transfer)...................................................................... 691
Table 18.10 List of LPC/FW Memory Access Commands .................................................. 693
Table 18.11 List of Factors that Prevents SYNC Field being Sent Back.............................. 697
Table 18.12 Receive Complete Interrupts and Error Interrupt.............................................. 710
Table 18.13 HIRQ Setting and Clearing Conditions............................................................. 712
Table 18.14 Host Address Example...................................................................................... 715
Section 19 A/D Converter
Table 19.1 Pin Configuration.................................................................................................. 719
Table 19.2 Analog Input Channels and Corresponding ADDR.............................................. 720
Table 19.3 A/D Conversion Time (Single Mode)................................................................... 726
Table 19.4 A/D Converter Interrupt Source............................................................................ 727
Section 21 Flash Memory (0.18-µm F-ZTAT Version)
Table 21.1 Comparison of Programming Modes.................................................................... 738
Table 21.2 Pin Configuration.................................................................................................. 744
Table 21.3 Register/Parameter and Target Mode ................................................................... 745
Table 21.4 Parameters and Target Modes............................................................................... 754
Table 21.5 On-Board Programming Mode Setting ................................................................. 764
Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 766
Table 21.7 Executable MAT................................................................................................... 784
Table 21.8 (1) Usable Area for Programming in User Program Mode................................. 785
Table 21.8 (2) Usable Area for Erasure in User Program Mode .......................................... 787
Table 21.8 (3) Usable Area for Programming in User Boot Mode....................................... 788
Table 21.8 (4) Usable Area for Erasure in User Boot Mode ................................................ 790
Table 21.9 Hardware Protection ............................................................................................. 792
Table 21.10 Software Protection........................................................................................... 793
Table 21.11 Inquiry and Selection Commands ..................................................................... 801
Table 21.12 Programming/Erasing Commands .................................................................... 813
Table 21.13 Status Code ....................................................................................................... 823
Rev. 3.00 Jul. 14, 2005 Page xlvii of xlviii