Renesas H8S Series Hardware Manual page 743

9. WRITEE clear command
When receiving the CMD8 address in an LPC/FW memory write cycle, the LPC clears the
WRITEE bit. Clearing the WRITEE bit avoids unintentional write accesses to the on-chip
RAM.
10. FLWAR set command
When receiving an FL address and the data of H'80 in an LPC/FW memory write cycle, the
LPC stores the FL address in FLWAR and set the BUFTRAN bit to 1 for the data write
command (flash memory). The BUFTRAN bit must be cleared to 0 to set data in FLWAR. If
the data of H'80 is written to the FL address, the data write command (flash memory) is
executed. The BUFTRAN bit must be cleared to 0 to set data in FLWAR.
Bits 4 to 0 in FLWARH store bits 19 to 15 of the transfer address and bits 7 to 0 in FLWARL
store the bits 14 to 7 of the transfer address. Bits 7 to 5 in FLWARH are fixed B'000.
11. Data write (flash memory)
When receiving an address which matches the FLWAR contents and data to be written to with
the BUFTRAN bit set to 1 in an LPC/FW memory write cycle, the LPC stores the data to be
written to the address selected by the RBUFAR contents. Byte, word, and longword transfers
are supported in FW memory write cycles. Since receiving the data write command to the flash
memory generates a memory access, confirm the LMCBUSY bit cleared to 0 after completion
of an LPC/FW memory write cycle. It is needed to decide the internal memory access status
since a wait state is not inserted in a write cycle. When the LMCBUSY is set, the commands
for an interrupt generation are prohibited. The BUFTRAN bit is not cleared after the data write
command is completed. To clear the BUFTRAN bit, the BUFTRAN clear command must be
executed. The addresses are compared between bits 7 to 0 in FLWARH and bits 22 to 15 of the
transfer address, or between bits 7 to 0 in FLWARH and bits 14 to 7 of the transfer address.
The lower six bits are not compared and are used as a buffer address without any change.
12. Flash Programming memory
When receiving the CMD9 address with the BUFTRAN set to 1 in an LPC/FW memory write
cycle, the LPC programs the flash memory. When receiving the flash memory programming
command, the LPC set the FLPI interrupt flag (one of the LMCI interrupt sources) and clears
the BUFTRAN bit at the same time. The slave must clear the FLPI bit to 0 after reading FLPI
= 1 on completion of programming the flash memory. The host reads LMCST1, waiting for the
FLPI bit cleared. After reading FLPI = 0 and checking the FLPERR bit, the host starts the next
command. During programming, the commands for a memory access or an interrupt
generation are prohibited.
13. BUFTRAN clear
When receiving the CMDA address in an LPC/FW memory write cycle, the LPC clears the
BUFTRAN bit. FLWAR can store another data after clearing the BUFTRAN bit.
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 695 of 986
REJ09B0098-0300