Page 1 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Rev. 1.00 May 09, 2008 Page ii of xxvi...
Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 4 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 5 Manual Application Note Examples of applications and The latest versions are available from our sample programs web site. Renesas Technical Preliminary report on the Update specifications of a product, document, etc. Rev. 1.00 May 09, 2008 Page v of xxvi...
Page 6 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name"...
Page 7 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] Bit Name Initial Value R/W...
Page 8 4. Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description Bus controller Clock pulse generator Interrupt controller Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer • Abbreviations other than those listed above Abbreviation Description ACIA...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 Features..........................1 1.1.1 Applications......................1 1.1.2 Overview of Functions....................2 List of Products........................7 Block Diagram........................8 Pin Descriptions........................9 1.4.1 Pin Assignments ....................... 9 1.4.2 Pin Assignment in Each Operating Mode............... 12 1.4.3 Pin Functions ......................19 Section 2 CPU......................29 Features..........................
Page 10 2.7.8 Memory Indirect@@aa:8 ................... 57 2.7.9 Effective Address Calculation ................58 Processing States........................60 Usage Note........................... 62 2.9.1 TAS Instruction ...................... 62 2.9.2 STM/LDM Instruction.................... 62 2.9.3 Notes on Using the Bit Operation Instruction............62 2.9.4 EEPMOV Instruction....................63 Section 3 MCU Operating Modes ...............65 Operating Mode Selection ....................
Page 11 Interrupt Exception Handling ....................93 Trap Instruction Exception Handling................... 93 Stack Status after Exception Handling................. 94 Usage Note........................... 95 Section 6 Interrupt Controller ................97 Features..........................97 Input/Output Pins......................... 99 Register Descriptions ......................100 6.3.1 Interrupt Control Registers A to D (ICRA to ICRD)..........101 6.3.2 Address Break Control Register (ABRKCR) ............
Page 12 6.8.4 Vector Address Switching ..................144 6.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode....145 6.8.6 Noise Canceler Switching..................145 6.8.7 IRQ Status Register (ISR)..................145 Section 7 Bus Controller (BSC) ................147 Register Descriptions ......................147 7.1.1 Bus Control Register (BCR) .................
Page 13 Change of Peripheral Function Pins................... 193 8.3.1 Port Control Register 0 (PTCNT0) ............... 193 8.3.2 Port Control Register 1 (PTCNT1) ............... 194 8.3.3 Port Control Register 2 (PTCNT2) ............... 195 Section 9 8-Bit PWM Timer (PWMU)..............197 Features..........................197 Input/Output Pins....................... 199 Register Descriptions ......................
Page 14 10.5 Operation ........................... 253 10.5.1 Basic Functions..................... 253 10.5.2 Synchronous Operation..................259 10.5.3 Buffer Operation....................261 10.5.4 PWM Modes......................265 10.5.5 Phase Counting Mode................... 269 10.6 Interrupts..........................274 10.6.1 Interrupt Source and Priority ................274 10.6.2 A/D Converter Activation..................275 10.7 Operation Timing.......................
Page 15 11.4 Operation ........................... 303 11.4.1 Timer Mode ......................303 11.4.2 Cycle Measurement Mode ..................305 11.5 Interrupt Sources........................ 310 11.6 Usage Notes ........................311 11.6.1 Conflict between TCMCNT Write and Count-Up Operation....... 311 11.6.2 Conflict between TCMMLCM Write and Compare Match........311 11.6.3 Conflict between TCMICR Read and Input Capture..........
Page 16 12.6.2 Compare-Match Count Mode ................339 12.7 TMR_Y and TMR_X Cascaded Connection ..............340 12.7.1 16-Bit Count Mode ....................340 12.7.2 Compare-Match Count Mode ................340 12.7.3 Input Capture Operation ..................341 12.8 Interrupt Sources........................ 343 12.9 Usage Notes ........................344 12.9.1 Conflict between TCNT Write and Counter Clear ..........
Page 17 14.3.5 Serial Mode Register (SMR) ................365 14.3.6 Serial Control Register (SCR) ................369 14.3.7 Serial Status Register (SSR) ................. 372 14.3.8 Smart Card Mode Register (SCMR)..............376 14.3.9 Bit Rate Register (BRR) ..................377 14.4 Operation in Asynchronous Mode ..................383 14.4.1 Data Transfer Format....................
Page 18 14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..............422 14.9.5 Relation between Writing to TDR and TDRE Flag ..........422 14.9.6 SCI Operations during Mode Transitions ............. 423 14.9.7 Notes on Switching from SCK Pins to Port Pins ..........426 14.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception............
Page 19 16.3.2 Receive Buffer Register (FRBR) ................459 16.3.3 Transmitter Shift Register (FTSR)................ 460 16.3.4 Transmitter Holding Register (FTHR)..............460 16.3.5 Divisor Latch H, L (FDLH, FDLL) ..............460 16.3.6 Interrupt Enable Register (FIER)................461 16.3.7 Interrupt Identification Register (FIIR)..............462 16.3.8 FIFO Control Register (FFCR)................
Page 20 17.4.5 Slave Receive Operation..................531 17.4.6 Slave Transmit Operation ..................535 17.4.7 IRIC Setting Timing and SCL Control ..............538 17.4.8 Noise Canceler...................... 540 17.4.9 Initialization of Internal State ................540 17.5 Interrupt Sources........................ 542 17.6 Usage Notes ........................543 17.6.1 Module Stop Mode Setting ...................
Page 21 19.4.8 Operation during Data Reception ................. 573 19.4.9 KCLK Fall Interrupt Operation ................574 19.4.10 First KCLK Falling Interrupt ................575 19.5 Usage Notes ........................579 19.5.1 KBIOE Setting and KCLK Falling Edge Detection ..........579 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission ....580 19.5.3 Module Stop Mode Setting ...................
Page 22 20.4.7 SCIF Control from LPC Interface................. 639 20.5 Interrupt Sources........................ 640 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ............. 640 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 ......641 20.6 Usage Note.........................
Page 23 21.4.6 SPI Flash Memory Write Operation Mode ............689 21.5 Reset Conditions ........................ 690 21.6 Interrupt Sources........................ 692 Section 22 A/D Converter..................693 22.1 Features..........................693 22.2 Input/Output Pins....................... 695 22.3 Register Descriptions ......................696 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ..........696 22.3.2 A/D Control/Status Register (ADCSR) ..............
Page 24 24.8 On-Board Programming Mode ..................743 24.8.1 Boot Mode ......................743 24.8.2 User Program Mode....................747 24.8.3 User Boot Mode....................756 24.8.4 Storable Areas for On-Chip Program and Program Data........760 24.9 Protection........................... 766 24.9.1 Hardware Protection ..................... 766 24.9.2 Software Protection....................767 24.9.3 Error Protection ....................
Page 25 26.8 Usage Notes ........................824 26.8.1 I/O Port Status....................... 824 26.8.2 Current Consumption when Waiting for Oscillation Stabilization ....... 824 Section 27 List of Registers ................825 27.1 Register Addresses (Address Order).................. 827 27.2 Register Bits........................848 27.3 Register States in Each Operating Mode ................864 27.4 Register Selection Condition .....................
Page 26 Rev. 1.00 May 09, 2008 Page xxvi of xxvi...
Page 27: Section 1 Overview
The core of each product in the H8S/2112R Group of CISC (complex instruction set computer) microcomputers is an H8S/2000 CPU, which has an internal 16-bit architecture. The H8S/2000 CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcomputers: H8/300, H8/300H, and H8S.
Page 28: Overview Of Functions
Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of this LSI in outline. Table 1.1 Overview of Functions Module/ Classification Function Description • Memory ROM lineup: Flash memory version H8S/2112R: 96 Kbytes • RAM capacity: 4 Kbytes •...
Page 29 Section 1 Overview Module/ Classification Function Description Mode 2: Single-chip mode operating (selected by driving the MD2 and MD0 pins low and MD1 mode pin high) Mode 4: Boot mode (selected by driving the MD2 high and MD1 and MD0 pins low) Mode 6: On-chip emulation mode (selected by driving the MD2 and MD1 pins high and the...
Page 30 Section 1 Overview Module/ Classification Function Description • 8-bit timers A/B × six channels Timer 8-bit PWM timer • Selectable from four clock sources (PWMU) • Cycle selectable for each channel • Supports 8-bit single pulse mode, 12-bit single pulse mode, 16- bit single pulse mode, and 8-bit pulse division mode.
Page 31 Section 1 Overview Module/ Classification Function Description • 8 bits × two channels (selectable from eight counter input Watchdog timer Watchdog clocks) timer • (WDT) Switchable between watchdog timer mode and interval timer mode • One channel (asynchronous mode) Serial interface Serial •...
Page 32 Section 1 Overview Module/ Classification Function Description • One channel High- • Supports communications between this LSI and SPI flash performance interface memory communication (FSI) • Capable of operating as a master • Supports LPC reset and LPC shut-down • One channel •...
Page 33: List Of Products
Indicates the product-specific number. H8S/2112R Indicates the type of ROM device. Indicates the product classification Microcomputer R indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Name Code Rev. 1.00 May 09, 2008 Page 7 of 954 REJ09B0462-0100...
Page 34: Block Diagram
Section 1 Overview Block Diagram H8S/2000CPU P10/WUE0 P11/WUE1 P12/WUE2 P13/WUE3 P14/WUE4 Clock pulse P15/WUE5 generator P16/WUE6 P17/WUE7 XTAL EXTAL (1 channel) (flasf memory) ETRST 16-bit TCM (3 channels) (1 channel) P30/LAD0 P31/LAD1 P32/LAD2 SCIF P33/LAD3 P34/LFRAME (1 channel) P35/LRESET P36/LCLK P37/SERIRQ P40/TMI0/TCMCYI0 Interrupt controller...
Page 35: Pin Descriptions
Section 1 Overview Pin Descriptions 1.4.1 Pin Assignments 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P74/AN4 P12/WUE2 P73/AN3 P11/WUE1 P72/AN2 P71/AN1 P10/WUE0 P70/AN0...
Page 36 Section 1 Overview AVref AVCC AVref AVCC AVSS AVSS H8S/2112R Group PLBG0176GA-A BP-176V (Top View) PE3* XTAL EXTAL PE4* PE1* ETRST PE2* INDEX : Non-connection pin (with solder ball) Note: * Not supported by the system development tool (emulator) Figure 1.4 Pin Assignments (BP-176V) Rev.
Page 37 Section 1 Overview AVCC AVref AVSS H8S/2112R Group PTLG0145JB-A (Top View) XTAL ETRST EXTAL INDEX : NC Pin Note: Not supported by the systen development tool (emulator) Figure 1.5 Pin Assignments (TLP-145V) Rev. 1.00 May 09, 2008 Page 11 of 954 REJ09B0462-0100...
Page 38: Pin Assignment In Each Operating Mode
Section 1 Overview 1.4.2 Pin Assignment in Each Operating Mode Table 1.3 Pin Assignment in Each Operating Mode Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) P43/TMI1/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWMU4B P47/PWMU5B  ...
Page 39 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) P92/IRQ0 P91/IRQ1 P90/IRQ2   PH2/CIRI   ETRST 28 (T) L2 (T) K4 (T) PE4*/ETMS PE3*/ETDO 30 (T) M1 (T) K2 (T) PE2*/ETDI 31 (T) M2 (T)
Page 40 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PF5/PWMU3A PF4/PWMU2A PF3/IRQ11/TMOX PF2/IRQ10/TMOY PF1/IRQ9/PWMU1A PF0/IRQ8/PWMU0A   51 (N) R7 (N) L6 (N) PG7/ExIRQ15/SCLD 52 (N) P7 (N) M7 (N) PG6/ExIRQ14/SDAD 53 (N) M8 (N) N6 (N)
Page 41 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0)   P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC     AVCC AVref    AVref P60/KIN0 P61/KIN1 P62/KIN2 P63/KIN3 P64/KIN4...
Page 42 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PC2/TIOCC0/TCLKA/WUE10 PC1/TIOCB0/WUE9 PC0/TIOCA0/WUE8     P17/WUE7 P16/WUE6 P15/WUE5 P14/WUE4 P13/WUE3 P12/WUE2 P11/WUE1       P10 WUE0 PB7/RTS/FSISS PB6/CTS/FSICK PB5/DTR/FSIDI...
Page 43 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) PB4/DSR/FSIDO PB3/DCD/PWMU1B PB2/RI/PWMU0B   PB1/LSCI PB0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK   P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1...
Page 44 Section 1 Overview Pin No. Pin Name Single-Chip Mode TFP- TLP- 144V 176V 145V Mode 2 (EXPE = 0)   XTAL EXTAL Notes: (N) in Pin No. indicates the pin is driven by NMOS push-pull/open drain and has 5 V input tolerance.
Page 45: Pin Functions
Section 1 Overview 1.4.3 Pin Functions Table 1.4 Pin Functions Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function Power 1, 36, 86 A1, J15, B1, M1, Input Power supply pins. Connect all supply P1, P2 these pins to the system power supply.
Page 46 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function Interrupts Input Nonmaskable interrupt request input pin IRQ15 to G2, H2, F1, G4, Input These pins request a maskable IRQ0 19 to 21, J4, J3, H4, G1, interrupt.
Page 47 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function 16-bit timer TCLKA Input Timer external clock input pins pulse unit TCLKB (TPU) TCLKC TCLKD TIOCA0 Input/ Input capture input/output TIOCB0 Output compare output/PWM output TIOCC0 pins for TGRA_0 to TGRD_0 TIOCD0 TIOCA1...
Page 48 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function Keyboard PS2AC Input/ Synchronous clock buffer PS2BC Output input/output pins for the control unit keyboard buffer control unit (PS2) PS2AD Input/ Data input/output pins for PS2BD Output the keyboard buffer control unit KIN15 to...
Page 49 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V Name and Function LAD3 to 124 to B9, A9, C9, B7, C8, D9, Input/ LPC command, address, Interface LAD0 Output and data input/output pins (LPC) LFRAME Input Input pin indicating LPC cycle start and forced termination of an abnormal LPC cycle...
Page 50 Section 1 Overview Pin No. TFP- BP-176V TLP- Type Symbol 144V 145V Name and Function A/D converter AN11 to 63 to 66, N11, R11, L8, K10, Input Analog input pins 75 to 68 P11, M11, N9, M10, P15, N13, L12, N13, R15, P14, M13, R14, P13,...
Page 51 Section 1 Overview Pin No. TFP- BP-176V TLP- Type Symbol 144V 145V Name and Function C/SMBus 2.0 SCL0 Input/ IIC/SMBUS clock I/O pins bus interface Output The output type is NMOS (IIC_0/SMBUS) open-drain. SDA0 Input/ IIC/SMBUS data I/O pins Output The output type is NMOS open-drain.
Page 52 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function I/O port P17 to 104 to 110, C15, 12, D10, C12, Input/ 8-bit input/output pins C14, B15, C13, D11, Output B14, A15, B13, A12, C13, B12 A13, B12 P27 to 96 to 103...
Page 53 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function I/O port PA7 to 33 to 35, N1, M4, L2, K3, Input/ 8-bit input/output pins 37 to 41 N2, R1, L1, N2, Output (The output type of PA7 to PA0 N3, R2, M2, M3, is NMOS push-pull.)
Page 54 Section 1 Overview Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator). 2. Following precautions are required on the reset signal that is applied to the ETRST pin. The reset signal should be applied to ETRST pin on power supply if the input voltage of the RES pin is low.
Page 55: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and provides maximum performance for realtime control.
Page 56: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
Section 2 CPU • High-speed operation  All frequently-used instructions execute in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)  16 ÷ 8-bit register-register divide: 12 states (DIVXU.B) ...
Page 57: Cpu Operating Modes
Section 2 CPU CPU Operating Modes This LSI operates in normal mode, which supports a maximum 16-Mbyte address space. The mode is selected by the mode pins. • Address Space Linear access to a 16-Mbyte maximum address space is provided. •...
Page 58 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. The operand is a 32-bit (longword), providing a 32-bit branch address.
Page 59: Address Space
Section 2 CPU Address Space Figure 2.3 shows a memory map for the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space. For details, refer to section 3, MCU Operating Modes. H'00000000 16-Mbyte Program area H'00FFFFFF Data area...
Page 60: Registers
Section 2 CPU Registers The H8S/2000 CPU has the internal registers shown in figure 2.4. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR)
Page 61: General Registers
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.5 illustrates the usage of the general registers.
Page 62: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Page 63: Condition-Code Register (Ccr)
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 64: Initial Values Of Cpu Registers
Section 2 CPU Initial Bit Name Value Description Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
Page 65: Data Formats
Section 2 CPU Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 66 Section 2 CPU Data Type Register Number Data Format Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats (2) Rev.
Page 67: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 68: Instruction Set
Section 2 CPU Instruction Set The H8S/2000 CPU has 65 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM* , STM* MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L...
Page 69: Table Of Instructions Classified By Function
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register)
Page 70 Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI.
Page 71 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 72 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 73 Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 74 Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 75 Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ∼...
Page 76 Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function  Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 77 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function  TRAPA Starts trap-instruction exception handling.  Returns from an exception-handling routine.  SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves general register or memory contents or immediate data to CCR or EXR.
Page 78 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+ → @ER6+ R4–1 →...
Page 79: Basic Instruction Formats
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows examples of instruction formats.
Page 80: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 81: Register Indirect With Displacement@(D:16, Ern) Or @(D:32, Ern)
Section 2 CPU 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand.
Page 82: Immediate#Xx:8, #Xx:16, Or #Xx:32
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Advanced Mode Data address 8 bits (@aa:8) H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address 2.7.6 Immediate#xx:8, #xx:16, or #xx:32...
Page 83: Memory Indirect@@Aa:8
Section 2 CPU 2.7.8 Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF).
Page 84: Effective Address Calculation
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses (EA) are calculated in each addressing mode. Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct(Rn) Operand is general register contents. Register indirect(@ERn) General register contents General register contents...
Page 85 Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * Normal mode is not available in this LSI. Rev.
Page 86: Processing States
Section 2 CPU Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.11 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 87 Section 2 CPU Program execution state SLEEP instruction with SLEEP LSON = 0 and instruction SSBY = 0 with LSON = 0, PSS = 0, and SSBY = 1 Request for exception End of handling exception handling Sleep mode Interrupt request Exception-handling state Software standby mode...
Page 88: Usage Note
The registers ER0, ER1 ER4, and ER5b must be used when using the TAS instruction. Note that the TAS instruction is not generated in the Renesas H8S, H8S/300 series C/C++ Compiler. When using the TAS instruction as a user-defined built-in function, the registers ER0, ER1 ER4, and ER5b must be used.
Page 89: Eepmov Instruction
Section 2 CPU 2.9.4 EEPMOV Instruction 1. The EEPMOV instruction is a block transfer instruction. The data with a start address shown in R5 and consists of bytes shown in R4L is transferred to the address shown in R6. R5 + R4L R6 + R4L 2.
Page 90 Section 2 CPU Rev. 1.00 May 09, 2008 Page 64 of 954 REJ09B0462-0100...
Page 91: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection.
Page 92: Register Descriptions
Section 3 MCU Operating Modes Register Descriptions The following registers are related to the operating modes. Table 3.2 Register Configuration Data Bus Register Name Abbreviation Initial Value Address Width  Mode control register MDCR H'FFC5 System control register SYSCR H'09 H'FFC4 Serial timer control register STCR...
Page 93: System Control Register (Syscr)
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space.
Page 94 Section 3 MCU Operating Modes Initial Bit Name Value Description KINWUE Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMRB), pull- up MOS control register (P6PCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y,...
Page 95: Serial Timer Control Register (Stcr)
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Initial Bit Name Value Description IICX2 C_2 Transfer Rate Select These bits control the IIC_2 operation.
Page 96 Section 3 MCU Operating Modes Initial Bit Name Value Description FLSHE Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (PCSR).
Page 97: System Control Register 3 (Syscr3)
Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Initial Bit Name Value Description — Reserved The initial value should not be changed. EIVS* Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table.
Page 98: Port Control Register 2 (Ptcnt2)
Section 3 MCU Operating Modes 3.2.5 Port Control Register 2 (PTCNT2) PTCNT2 selects SCI input/output inversion and controls the port specification. Initial Bit Name Value Description 7 to 5 — All 0 Reserved The initial value should not be changed. TxD1RS 0: TxD1 direct output 1: TxD1 inverted output...
Page 99: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in either advanced mode or single-chip mode. The on-chip ROM is enabled. Address Map Figures 3.1 shows the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode...
Page 100 Section 3 MCU Operating Modes Rev. 1.00 May 09, 2008 Page 74 of 954 REJ09B0462-0100...
Page 101: Section 4 Resets
Section 4 Resets Section 4 Resets Types of Resets There are three types of resets: a pin reset, power-on reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized by a reset. Figure 4.1 shows the reset targets to be initialized.
Page 102: Input/Output Pin
Section 4 Resets Note that some registers are not initialized by any of the resets. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses with the reset exception handling. At this time, the T bit in EXR is cleared to 0 and the I bits in EXR and CCR are set to 1.
Page 103: Register Descriptions
Section 4 Resets Register Descriptions This LSI has the following registers for resets. Table 4.3 Register Configuration Initial Data Bus Register Name Abbreviation Value Address Width Reset status register RSTSR H'00 H'FB35 System control register SYSCR H'09 H'FFC4 Timer control/status register_0 TCSR_0 H'00 H'FFA8...
Page 104: System Control Register (Syscr)
Section 4 Resets 4.3.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. Initial Bit Name Value...
Page 105 Section 4 Resets Initial Bit Name Value Description KINWUE Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pull-up MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC, TCORA_X, TCORB_X, TCONRI, and TCONRS) of...
Page 106: Timer Control/Status Register (Tcsr)
Section 4 Resets 4.3.3 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT of the watchdog timer, and the timer mode. • TCSR_0 Initial Bit Name Value Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00).
Page 107 Section 4 Resets Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz is enclosed in parentheses. CKS0 000: φ/2 (frequency: 25.6 µs) 001: φ/64 (frequency: 819.2 µs) 010: φ/128 (frequency: 1.6 µs) 011: φ/512 (frequency: 6.6 µs)
Page 108 Section 4 Resets Initial Bit Name Value R/W Description WT/IT Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer 0: Interval timer mode 1: Watchdog timer mode Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
Page 109: Pin Reset
Section 4 Resets Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz and φSUB = 32.768 kHz is CKS0 enclosed in parentheses. When PSS = 0 000: φ/2 (frequency: 25.6 µs) 001: φ/64 (frequency: 819.2 µs)
Page 110: Power-On Reset
Section 4 Resets Power-on Reset This is an internal reset generated by the power-on reset. A power-on with the RES pin held high generates the power-on reset. When VCC exceeds the level of Vpor, the power-on reset is canceled after the elapse of the specified time (the power-on reset time). The power-on reset time is the stabilization time for the external power supply and LSI.
Page 111: Watchdog Timer Reset
Section 4 Resets After the VCC is turned on with the RES pin held low, namely in the state of pin reset, if the RES pin is driven high in the state that the VCC stays higher than the level of Vpor, the power-on reset function is disabled and a reset exception handling starts before entering the power-on reset time.
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Page 113: Section 5 Exception Handling
Section 5 Exception Handling Section 5 Exception Handling Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 114: Exception Sources And Exception Vector Table
Section 5 Exception Handling Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 5.2 and table 5.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode.
Page 115 Section 5 Exception Handling Vector Addresses Vector Exception Source Number Advanced Mode Internal interrupt* H'000060 to H'000063   H'000074 to H'000077 Reserved for system use H'000078 to H'00007B Reserved for system use H'00007C to H'00007F External interrupt WUE7 to WUE0 H'000080 to H'000083 External interrupt WUE15 to WUE8 33 H'000084 to H'000087...
Page 116 Section 5 Exception Handling Table 5.3 Exception Handling Vector Table (Extended Vector Mode) Vector Addresses Vector Exception Source Number Advanced Mode Reset H'000000 to H'000003 Reserved for system use H'000004 to H'000007  H'00000C to H'00000F Reserved for system use H'000010 to H'000013 Reserved for system use H'000014 to H'000017...
Page 117: Reset
Section 5 Exception Handling Vector Vector Addresses Number Exception Source Normal Mode Internal interrupt* H'000088 to H'00008B   H'0000DC to H'0000DF External interrupt IRQ8 H'0000E0 to H'0000E3 IRQ9 H'0000E4 to H'0000E7 IRQ10 H'0000E8 to H'0000EB IRQ11 H'0000EC to H'0000EF IRQ12 H'0000F0 to H'0000F3 IRQ13...
Page 118: Interrupts Immediately After Reset
Section 5 Exception Handling Figure 5.1 shows an example of the reset sequence. Vector Internal Prefetch of first fetch processing program instruction φ Power-on internal reset signal Internal address bus (1) U (1) L Internal read signal Internal write signal High Internal data bus (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002...
Page 119: Interrupt Exception Handling
Section 5 Exception Handling Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority.
Page 120: Stack Status After Exception Handling
Section 5 Exception Handling Stack Status after Exception Handling Figure 5.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (24 bits) Figure 5.2 Stack Status after Exception Handling Rev. 1.00 May 09, 2008 Page 94 of 954 REJ09B0462-0100...
Page 121: Usage Note
Section 5 Exception Handling Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even.
Page 122 Section 5 Exception Handling Rev. 1.00 May 09, 2008 Page 96 of 954 REJ09B0462-0100...
Page 123: Section 6 Interrupt Controller
Section 6 Interrupt Controller Section 6 Interrupt Controller Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks.
Page 124 Section 6 Interrupt Controller EIVS SYSCR3 INTM1, INTM0 SYSCR NMIEG NMI input NMI input Interrupt request IRQ input IRQ input Vector number Priority level ISCR determination KMIMR WUEMR I, UI KIN input KIN, WUE WUE input input Internal interrupt sources WOVI0 to IBFI3 Interrupt controller [Legend]...
Page 125: Input/Output Pins
Section 6 Interrupt Controller Input/Output Pins Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Pin Configuration Pin Name Function Input Nonmaskable external interrupt pin Rising edge or falling edge can be selected IRQ15 to IRQ0, Input Maskable external interrupt pins ExIRQ15 to ExIRQ6 Rising-edge, falling-edge, or both-edge detection, or level- sensing, can be selected individually for each pin.
Page 126: Register Descriptions
Section 6 Interrupt Controller Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). Table 6.2 Register Configuration Data Bus...
Page 127: Interrupt Control Registers A To D (Icra To Icrd)
Section 6 Interrupt Controller Data Bus Register Name Abbreviation Initial Value Address Width Wake-up event interrupt mask WUEMRB H'FF H'FE44 register B Wake-up sense control register A WUESCRA H'00 H'FE84 (WUE15 to WUE8) Wake-up sense control register B WUESCRB H'00 H'FE96 (WUE7 to WUE0) Wake-up input interrupt status...
Page 128 Section 6 Interrupt Controller Table 6.3 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Register Bit Name ICRA ICRB ICRC ICRD ICRn7 IRQ0 A/D converter SCIF IRQ8 to IRQ11 ICRn6 IRQ1 TCM_0, TCM_1, SCI_1 IRQ12 to IRQ15 TCM_2 ICRn5...
Page 129: Address Break Control Register (Abrkcr)
Section 6 Interrupt Controller 6.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit Name Initial Value R/W Description Undefined Condition Match Flag Address break source flag.
Page 130: Break Address Registers A To C (Bara To Barc)
Section 6 Interrupt Controller 6.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. •...
Page 131: Irq Sense Control Registers (Iscr16H, Iscr16L, Iscrh, Iscrl)
Section 6 Interrupt Controller 6.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. • ISCR16H Bit Name Initial Value R/W Description IRQ15SCB IRQn Sense Control B...
Page 132 Section 6 Interrupt Controller • ISCR16L Bit Name Initial Value Description IRQ11SCB IRQn Sense Control B IRQ11SCA IRQn Sense Control A IRQ10SCB 00: Interrupt request generated at low level of IRQn IRQ10SCA or ExIRQn input IRQ9SCB 01: Interrupt request generated at falling edge of IRQ9SCA IRQn or ExIRQn input IRQ8SCB...
Page 133 Section 6 Interrupt Controller • ISCRL Bit Name Initial Value Description IRQ3SCB IRQn Sense Control B IRQ3SCA IRQn Sense Control A IRQ2SCB 00: Interrupt request generated at low level of IRQn IRQ2SCA input IRQ1SCB 01: Interrupt request generated at falling edge of IRQ1SCA IRQn input IRQ0SCB...
Page 134: Irq Enable Registers (Ier16, Ier)
Section 6 Interrupt Controller 6.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Name Initial Value Description IRQ15E IRQn Enable IRQ14E The IRQn interrupt request is enabled when this bit is 1.
Page 135: Irq Status Registers (Isr16, Isr)
Section 6 Interrupt Controller 6.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. • ISR16 Bit Name Initial Value Description IRQ15F R/(W)* [Setting condition] IRQ14F R/(W)* When the interrupt source selected by the ISCR16 registers occurs IRQ13F R/(W)*...
Page 136 Section 6 Interrupt Controller • ISR Bit Name Initial Value Description IRQ7F R/(W)* [Setting condition] IRQ6F R/(W)* When the interrupt source selected by the ISCR registers occurs IRQ5F R/(W)* [Clearing conditions] IRQ4F R/(W)* • When writing 0 to IRQnF flag after reading IRQ3F R/(W)* IRQnF = 1...
Page 137: Irq Sense Port Select Registers 16 (Issr16) Irq Sense Port Select Registers (Issr)
Section 6 Interrupt Controller 6.3.7 IRQ Sense Port Select Registers 16 (ISSR16) IRQ Sense Port Select Registers (ISSR) The ISSR16 and ISSR registers select the external interrupt input for IRQ15 to IRQ0 from the pins IRQ15 to IRQ7 and ExIRQ15 to ExIRQ7. •...
Page 138: Keyboard Matrix Interrupt Mask Registers (Kmimra, Kmimrb) Wake-Up Event Interrupt Mask Registers (Wuemra, Wuemrb)
Section 6 Interrupt Controller 6.3.8 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMRB) Wake-up Event Interrupt Mask Registers (WUEMRA, WUEMRB) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE0). •...
Page 139 Section 6 Interrupt Controller • WUEMRA Bit Name Initial Value Description WUEMR15 Wake-Up Event Interrupt Mask WUEMR14 These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). WUEMR13 0: Enables a wake-up event input interrupt request WUEMR12 1: Disables a wake-up event input interrupt request WUEMR11...
Page 140 Section 6 Interrupt Controller Figure 6.2 shows the relation between the IRQ7 and IRQ6 interrupts, KMIMRA and KMIMRB in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 6.3. KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) IRQ6 internal...
Page 141 Section 6 Interrupt Controller In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 bits is cleared to 0. If the KIN7 to KIN0 pins or KIN15 to KIN8 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing.
Page 142: Wake-Up Sense Control Register (Wuescra, Wuescrb) Wake-Up Input Interrupt Status Register (Wuesra, Wuesrb) Wake-Up Enable Register (Wueer)
Section 6 Interrupt Controller 6.3.9 Wake-Up Sense Control Register (WUESCRA, WUESCRB) Wake-Up Input Interrupt Status Register (WUESRA, WUESRB) Wake-Up Enable Register (WUEER) WUESCR, WUESR, and WUEER select the interrupt source of the wake-up event interrupt inputs (WUE15 to WUE0) and enable or disable the interrupt request flag registers and interrupts. •...
Page 143 Section 6 Interrupt Controller • WUESRA Bit Name Initial Value Description WUE15F R/(W)* Wake-Up Input Interrupt (WUE15 to WUE8) Request Flag Register WUE14F R/(W)* These bits are status flags that indicate that wake- WUE13F R/(W)* up input interrupts (WUE15 to WUE8) are WUE12F R/(W)* requested.
Page 144 Section 6 Interrupt Controller • WUEER Bit Name Initial Value Description WUEAE WUE15 to WUE8 Enable The WUE interrupt request is enabled when this bit is 1. 0: Wake-up input interrupt request is disabled 1: Wake-up input interrupt request is enabled WUEBE WUE7 to WUE0 Enable The WUE interrupt request is enabled when this bit...
Page 145: Interrupt Sources
Section 6 Interrupt Controller Interrupt Sources 6.4.1 External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 146 Section 6 Interrupt Controller A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 6.4. IRQnE IRQnSCA, IRQnSCB IRQnF IRQn IRQn interrupt Edge/level request ISSm detection circuit ExIRQn Clear signal n = 15 to 7 m = 15 to 7 Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit.
Page 147 Section 6 Interrupt Controller • Extended vector mode (EIVS = 1 in SYSCR3)  Interrupts KIN15 to KIN8 and KIN7 to KIN0, each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address. ...
Page 148: Internal Interrupt Sources
Section 6 Interrupt Controller A block diagram of interrupts WUE15 to WUE0 is shown in figure 6.5. WUEMRn Rising/falling-edge selection and interrupt WUEn interrupt request enable/disable circuit WUEn input Clear signal n = 15 to 0 Figure 6.5 Block Diagram of Interrupts WUE15 to WUE0 6.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features:...
Page 149: Interrupt Exception Handling Vector Tables
Section 6 Interrupt Controller Interrupt Exception Handling Vector Tables Tables 6.5 and 6.6 list interrupt exception handling sources, vector addresses, and interrupt priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for the vector addresses by the EIVS bit in system control register 3 (SYSCR3). For default priorities, the lower the vector number, the higher the priority.
Page 150 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TPU_0 TGI0A (TGR0A input H'000088 ICRD3 High capture/compare match) TGI0B (TGR0B input H'00008C capture/compare match) TGI0C (TGR0C input H'000090 capture/compare match) TGI0D (TGR0D input H'000094 capture/compare match) TGI0V (Overflow 0)
Page 151 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority External pin IRQ8 H'0000E0 ICRD7 High IRQ9 H'0000E4 IRQ10 H'0000E8 IRQ11 H'0000EC IRQ12 H'0000F0 ICRD6 IRQ13 H'0000F4 IRQ14 H'0000F8 IRQ15 H'0000FC TMR_0 CMIA0 (Compare match A) H'000100 ICRB3 CMIB0 (Compare match B)
Page 152 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority KBIA (Reception completion A) H'000180 ICRB0 High KBIB (Reception completion B) H'000184 H'000188 — — Reserved for system use KBTIA (Transmission completion A)/ H'00018C ICRB0 KBCA (1st KCLKA) KBTIB (Transmission completion B)/...
Page 153 Section 6 Interrupt Controller Table 6.6 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Origin of Vector Address Interrupt Vector Source Number Name Advanced Mode Priority External pin H'00001C — High IRQ0 H'000040 ICRA7 IRQ1 H'000044 ICRA6 IRQ2 H'000048 ICRA5 IRQ3...
Page 154 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority TPU_2 TGI2A (TGR2A input H'0000AC ICRD1 High capture/compare match) TGI2B (TGR2B input H'0000B0 capture/compare match) TGI2V (Overflow 1) H'0000B4 TGI2U (Underflow 2) H'0000B8 — Reserved for system use H'0000BC —...
Page 155 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority — Reserved for system use H'00011C — High TMR_X CMIAY (Compare match A) H'000120 ICRB1 TMR_Y CMIBY (Compare match B) H'000124 OVIY (Overflow) H'000128 ICIX (Input capture) H'00012C CMIAX (Compare match A)
Page 156 Section 6 Interrupt Controller Origin of Vector Address Interrupt Vector Source Name Number Advanced Mode Priority OBEI (ODR1 to 4 transmission H'0001A8 ICRC1 High completion) IBFI4 (IDR4 reception completion) H'0001AC ERRI (Transfer error, etc.) H'0001B0 IBFI1 (IDR1 reception completion) H'0001B4 IBFI2 (IDR2 reception completion) H'0001B8 IBFI3 (IDR3 reception completion)
Page 157: Interrupt Control Modes And Interrupt Operation
Section 6 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state. The interrupt control mode is selected by SYSCR.
Page 158 Section 6 Interrupt Controller Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 6.8 shows the interrupts selected in each interrupt control mode.
Page 159: Interrupt Control Mode 0
Section 6 Interrupt Controller Table 6.9 shows operations and control signal functions in each interrupt control mode. Table 6.9 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Setting 3-Level Control Interrupt Default Priority Control Mode INTM1 INTM0 Determination Ο...
Page 160 Section 6 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Hold pending An interrupt with interrupt...
Page 161: Interrupt Control Mode 1
Section 6 Interrupt Controller 6.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. •...
Page 162 Section 6 Interrupt Controller Figure 6.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Page 163 Section 6 Interrupt Controller Program execution state Interrupt generated? Hold pending An interrupt with interrupt control level 1? IRQ0 IRQ0 IRQ1 IRQ1 IBFI3 IBFI3 I = 0 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine Figure 6.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev.
Page 164: Interrupt Exception Handling Sequence
Section 6 Interrupt Controller 6.6.3 Interrupt Exception Handling Sequence Figure 6.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Page 165: Interrupt Response Times
Section 6 Interrupt Controller 6.6.4 Interrupt Response Times Table 6.10 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 6.10 Interrupt Response Times Execution Status Advanced Mode Interrupt priority determination* Number of wait states until executing instruction...
Page 166: Address Breaks
Section 6 Interrupt Controller Address Breaks 6.7.1 Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed.
Page 167: Operation
Section 6 Interrupt Controller 6.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority.
Page 168 Section 6 Interrupt Controller (1) Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal Vector Internal Instruction fetch fetch fetch fetch fetch operation fetch operation fetch Stack save φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318...
Page 169: Usage Notes
Section 6 Interrupt Controller Usage Notes 6.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 170: Instructions For Disabling Interrupts
Section 6 Interrupt Controller 6.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 171: External Interrupt Pin In Software Standby Mode And Watch Mode
Section 6 Interrupt Controller 6.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ6, KIN15 to KIN0, and WUE15 to WUE0) are used as external input pins in software standby mode or watch mode, the pins should not be left floating.
Page 172 Section 6 Interrupt Controller Rev. 1.00 May 09, 2008 Page 146 of 954 REJ09B0462-0100...
Page 173: Section 7 Bus Controller (Bsc)
Section 7 Bus Controller (BSC) Section 7 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. Register Descriptions The bus controller has the following registers.
Page 174: Wait State Control Register (Wscr)
Section 7 Bus Controller (BSC) 7.1.2 Wait State Control Register (WSCR) Initial Bit Name Value Description 7, 6 — All 1 Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed.
Page 175: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 lists the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port input data register (PIN) used to read the pin states.
Page 176 Section 8 I/O Ports Table 8.1 Port Functions LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler WUE7   Port 1 General I/O port also WUE6  functioning as WUE5 ...
Page 177 Section 8 I/O Ports LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler    Port 4 General I/O PWMU5B port also  PWMU4B functioning as TCMCKI2/ PWMU3B PWMU_B TCMMCI2 output, TCM...
Page 178 Section 8 I/O Ports LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler      Port 7 General input P77/AN7 port also   P76/AN6 functioning as ...
Page 179 Section 8 I/O Ports LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler KIN15     Port A General I/O port also KIN14  functioning as KIN13 ...
Page 180 Section 8 I/O Ports LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler    Port D General I/O port also   functioning as   A/D converter analog input ...
Page 181 Section 8 I/O Ports LED Drive Function Input Pull- Capability On-Chip up MOS (5 mA Sink Noise Port Description Input Output Function Current) Canceler ExIRQ15    Port G General I/O PG7/SCLD port also ExIRQ14  PG6/SDAD functioning as ExIRQ13 ...
Page 182: Register Descriptions
Section 8 I/O Ports Register Descriptions Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Registers Number Port of Pins DDR NCMC NCCS NOCR Port 1      Port 2    ...
Page 183: Data Direction Register (Pnddr) (N = 1 To 6, 8, 9, A To D, And F To H)
Section 8 I/O Ports 8.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to H) DDR specifies the port input or output for each bit. The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are reserved.
Page 184: Data Register (Pndr) (N = 1 To 6, 8, And 9)
Section 8 I/O Ports 8.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9) DR is a register that stores output data of the pins to be used as the general output port. Since the P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five bits in P5DR and the upper one bit in P8DR are reserved.
Page 185: Pull-Up Mos Control Register (Pnpcr) (N = 1 To 3, 6, 9, B To D, F, And H)
Section 8 I/O Ports 8.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 6, 9, B to D, F, and H) PCR is a register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in the input state, the input pull-up MOS corresponding to the bit in PCR is turned on.
Page 186: Output Data Register (Pnodr) (N = A To D And F To H)
Section 8 I/O Ports • Ports B to D, F, and H Table 8.3 Input Pull-Up MOS State (2) Port Pin State Reset Software Standby Mode Other Operation Ports B to D, Port output F, and H Port input On/Off [Legend] Off: The input pull-up MOS is always off.
Page 187: Noise Canceler Enable Register (Pnnce) (N = 4, 6, C, And G)
Section 8 I/O Ports Noise Canceler Enable Register (PnNCE) (n = 4, 6, C, and G) 8.1.6 NCE enables or disables the noise cancel circuit at port n pins in bit units. Bit Name Initial Value Description Pn7NCE Noise cancel circuit is enabled when a bit in this register is set to 1, and the pin setting state is Pn6NCE fetched in P4DR, P6DR, or PnPIN in the sampling...
Page 188: Noise Cancel Cycle Setting Register (Pnnccs) (N = 4, 6, C, And G)
Section 8 I/O Ports Noise Cancel Cycle Setting Register (PnNCCS) (n = 4, 6, C, and G) 8.1.8 NCCS controls the sampling cycles of the noise canceler. Bit Name Initial Value Description 7 to 3  Undefined Reserved The read value is undefined. The write value should always be 0.
Page 189: Port Nch-Od Control Register (Pnnocr) (N = C, D, F, G, And H)
Section 8 I/O Ports P4n input P6n input PCn input PGn input 1 expected P4n input P6n input PCn input PGn input 0 expected P4n input P6n input PCn input PGn input (n = 7 to 0) Figure 8.2 Schematic View of Noise Cancel Operation Port Nch-OD Control Register (PnNOCR) (n = C, D, F, G, and H) 8.1.9 The individual bits of NOCR specify output driver type for the pins of port n that is specified as...
Page 190: Mos State Of Output Buffer
Section 8 I/O Ports 8.1.10 MOS State of Output Buffer The pin function is switched according to the setting of the PORTS bit in PTCNT2. (Ports C, D, F, G, and H) PORTS = 0  NOCR Driver at Vss Driver at Vcc Input pull-up MOS*...
Page 191: Pin Functions
Section 8 I/O Ports Pin Functions 8.2.1 Port 1 P17/WUE7, P16/WUE6, P15/WUE5, P14/WUE4, P13/WUE3, P12/WUE2, P11/WUE1, P10/WUE0 The pin function is switched as shown below according to the P1nDDR bit setting. When the WUEMRn bit in WUEMRB of the interrupt controller is cleared to 0, the pin functions as the WUEn input pin.
Page 192: Port 3
Section 8 I/O Ports 8.2.3 Port 3 P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, and the SCIFE bit in HICR5, the LPC4E bit in HICR4, and the LPC3E to LPC1E bits in HICR0 of LPC, and the P3nDDR bit.
Page 193: Port 4
Section 8 I/O Ports 8.2.4 Port 4 P47/PWMU5B The pin function is switched as shown below according to the combination of the PWM5E bit in PWMOUTCR of PWMU_B, and the P47DDR bit. P47DDR  PWM5E Pin function P47 input pin P47 output pin PWMU5B output pin P46/PWMU4B...
Page 194 Section 8 I/O Ports P44/TMO1/PWMU2B/TCMCYI2 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCR of TMR_1, the PWM2E bit in PWMOUTCR of PWMU_B, and the P44DDR bit. When the TCMIPE bit in TCMIER_2 of TCM_2 is set to 1, the pin functions as the TCMCY2 input pin. OS3 to OS0 All 0 Any of them is 1...
Page 195 Section 8 I/O Ports P41/TMO0/TCMCKI0/TCMMCI0 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_0 and the P41DDR bit. When an external clock is selected by the CKS2 to CKS0 bits in TCMCR of TCM_0, the pin functions as the TCMCKI0 input pin.
Page 196: Port 5
Section 8 I/O Ports 8.2.5 Port 5 P52/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P52DDR bit.  P52DDR Pin function P52 input pin P52 output pin SCL0 I/O pin Note: The output format for SCL0 is NMOS output only and direct bus drive is possible.
Page 197: Port 6
Section 8 I/O Ports 8.2.6 Port 6 P67/IRQ7/KIN7 When the KMIM7 bit in KMIMR of the interrupt controller is cleared to 0, this pin functions as the KIN7 input pin. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin.
Page 198: Port 7
Section 8 I/O Ports 8.2.7 Port 7 P77/AN7, P76/AN6, P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0 Pin function ANn/P7n input (n = 7 to 0) 8.2.8 Port 8 P86/IRQ5/SCK1 The pin function is switched as shown below according to the combination of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR of SCI_1, and the P86DDR bit.
Page 199 Section 8 I/O Ports P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in IER of the interrupt controller is set to 1, this pin functions as the IRQ3 input pin.
Page 200 Section 8 I/O Ports P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 of LPC and the P81DDR bit. FGA20E  P81DDR Pin function P81 input pin P81 output pin GA20 output pin P80/PME The pin function is switched as shown below according to the combination of the PMEE bit in...
Page 201: Port 9
Section 8 I/O Ports 8.2.9 Port 9 P97/IRQ15/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P97DDR bit. When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin functions as the IRQ15 input pin.
Page 202: Port A
Section 8 I/O Ports 8.2.10 Port A PA7/KIN15, PA6/KIN14, PA1/KIN9, PA0/KIN8 The pin function is switched according to the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin functions as the KINm input pin. PAnDDR Pin function PAn input pin...
Page 203: Port B
Section 8 I/O Ports 8.2.11 Port B PB7/RTS/FSISS The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1 of FSI and the PB7DDR bit. SCIFOE in the following table is expressed by the following logical expression.
Page 204 Section 8 I/O Ports PB4/DSR/FSIDO The pin function is switched as shown below according to the combination of the FSIE bit in FSICR1 of FSI and the PB4DDR bit. FSIE  PB4DDR Pin function PB4 input pin PB4 output pin FSIDO output pin DSR input pin PB3/DCD/PWMU1B...
Page 205 Section 8 I/O Ports PB1/LSCI The pin function is switched as shown below according to the combination of the LSCIE bit in HICR0 of LPC and the PB1DDR bit. LSCIE  PB1DDR Pin function PB1 input pin PB1 output pin LSCI output pin PB0/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in...
Page 206: Port C
Section 8 I/O Ports 8.2.12 Port C PC7/WUE15/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting, the TPSC2 to TPSC0 bits in TCR_0 of TPU, and the PC7DDR bit. When the WUEMR15 bit in WUEMR of the interrupt controller is cleared to 0, this pin functions as the WUE15 input pin.
Page 207 Section 8 I/O Ports PC5/WUE13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting, the TPSC2 to TPSC0 bits in TCR_0 or TCR_2 of TPU, and the PC5DDR bit. When the WUEMR13 bit in WUEMRA of the interrupt controller is cleared to 0, this pin functions as the WUE13 input pin.
Page 208 Section 8 I/O Ports PC3/WUE11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting, the TPSC2 to TPSC0 bits in any of TCR_0 to TCR_2 of TPU, and the PC3DDR bit. When the WUEMR11 bit in WUEMRA of the interrupt controller is cleared to 0, this pin functions as the WUE11 input pin.
Page 209 Section 8 I/O Ports PC1/WUE9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting and the PC1DDR bit. When the WUEMR9 bit in WUEMRA of the interrupt controller is cleared to 0, this pin functions as the WUE9 input pin.
Page 210: Port D
Section 8 I/O Ports 8.2.13 Port D PD7, PD6, PD5, PD4 The pin function is switched as shown below according to the PDnDDR bit. PDnDDR Pin function PDn input pin PDn output pin (n = 7 to 4) PD3/AN11, PD2/AN10, PD1/AN9, PD0/AN8 The pin function is switched as shown below according to the PDnDDR bit.
Page 211: Port E
Section 8 I/O Ports 8.2.14 Port E PE4/ETMS, PE3/ETDO, PE2/ETDI, PE1/ETCK The pin function is switched as shown below according to the operating mode. Operating mode On-chip emulation mode Single-chip mode Pin function Emulator input/output PEn input (n = 4 to 1) Note: Pins PE4 to PE1 are not supported by the system development tool (emulator).
Page 212: Port F
Section 8 I/O Ports 8.2.15 Port F PF7/PWMU5A, PF6/PWMU4A, PF5/PWMU3A, PF4/PWMU2A The pin function is switched as shown below according to the combination of the PWMmE bit in PWMOUTCR of PWMU_A and the PFnDDR bit. PFnDDR  PWMmE Pin function PFn input pin PFn output pin PWMUmA output pin...
Page 213 Section 8 I/O Ports PF1/IRQ9/PWMU1A The pin function is switched as shown below according to the combination of the PWM1E bit in PWMOUTCR of PWMU_A and the PF1DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin.
Page 214: Port G
Section 8 I/O Ports 8.2.16 Port G PG7/SCLB/ExIRQ15 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_2, the IIC2AS bit in IIC2BS of PTCNT1, and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
Page 215 Section 8 I/O Ports PG5/SCLC/ExIRQ13 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_2, the IIC2AS bit in IIC2BS of PTCNT1, and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
Page 216 Section 8 I/O Ports PG3/SCLB/ExIRQ11 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_2, the IIC2AS bit in IIC2BS of PTCNT1, and the PG3DDR bit. When the ISS11 bit in ISSR16 is set to 1 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin.
Page 217 Section 8 I/O Ports PG1/SCLA/ExIRQ9/TMIY The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_2, the IIC2AS bit in IIC2BS of PTCNT1, and the PG1DDR bit. TMRIY and TMCIY are multiplexed as the TMIY input pin.
Page 218: Port H
Section 8 I/O Ports 8.2.17 Port H PH5, PH4, PH3 The pin function is switched as shown below according to the PHnDDR bit. PHnDDR Pin function PHn input pin PHn output pin (n = 5 to 3) PH2/CIRI The pin function is switched as shown below according to the combination of the CIRE bit in CCR1 of CIR and the PH2DDR bit.
Page 219: Change Of Peripheral Function Pins
Section 8 I/O Ports Change of Peripheral Function Pins For the external sub-clock input and IIC input/output, the multi-function I/O ports can be changed. The external interrupt can be changed by the setting of ISSR16 and ISSR. I/O ports that also function as the external sub-clock input pin are changed by the setting of PTCNT0.
Page 220: Port Control Register 1 (Ptcnt1)
Section 8 I/O Ports 8.3.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IIC_2 input/output pins. Bit Name Initial Value Description IIC2BS These bits select input/output pins for IIC_2 IIC2AS IIC2BS IIC2AS Selects PG1/SCLA and PG0/SDAA Selects PG3/SCLB and PG2/SDAB Selects PG5/SCLC and...
Page 221: Port Control Register 2 (Ptcnt2)
Section 8 I/O Ports 8.3.3 Port Control Register 2 (PTCNT2) PTCNT2 selects SCI input/output conversion and controls the port specification. Bit Name Initial Value R/W Description  7 to 5 All 0 Reserved The initial value should not be changed. TxD1RS 0: TxD1 direct output 1: TxD1 inverted output...
Page 222 Section 8 I/O Ports Rev. 1.00 May 09, 2008 Page 196 of 954 REJ09B0462-0100...
Page 223: Section 9 8-Bit Pwm Timer (Pwmu)
Section 9 8-Bit PWM Timer (PWMU) Section 9 8-Bit PWM Timer (PWMU) This LSI has two channels of 8-bit PWM timers, A and B (PWMU_A and PWMU_B). Each PWMU outputs 6 PWM waveforms. Each of the PWM channels of a PWMU can operate independently.
Page 224 Section 9 8-Bit PWM Timer (PWMU) • 8-bit pulse division mode Operable at a maximum carrier frequency of 1.57 MHz (at 25 MHz operation) Pulse output settable with a duty cycle from 0/16 to 15/16 PWM output enable/disable control, and selection of direct or inverted PWM output Figure 9.1 shows a block diagram of the PWMU.
Page 225: Input/Output Pins
Section 9 8-Bit PWM Timer (PWMU) Input/Output Pins Table 9.1 shows the PWMU pin configuration. Table 9.1 Pin Configuration Channel Pin Name Function Channel A PWMU0A Output PWM pulse output (8-bit single pulse, 8-bit pulse division) PWMU1A Output PWM pulse output (8/12/16-bit single pulse, 8-bit pulse division) PWMU2A Output...
Page 226: Register Descriptions
Section 9 8-Bit PWM Timer (PWMU) Register Descriptions The PWMU has the following registers. Table 9.2 Register Configuration Data Initial Channel Register Name Abbreviation Value Address Width Channel A PWM clock control register_A PWMCKCR_A H'00 H'FD0C PWM output control register_A PWMOUTCR_A R/W H'00 H'FD0D PWM mode control register_A PWMMDCR_A R/W...
Page 227 Section 9 8-Bit PWM Timer (PWMU) Data Initial Channel Register Name Abbreviation Value Address Width Channel B PWM clock control register_B PWMCKCR_B H'00 H'FD1C PWM output control register_B PWMOUTCR_B R/W H'00 H'FD1D PWM mode control register_B PWMMDCR_B R/W H'00 H'FD1E PWM phase control register_B PWMPCR_B H'00 H'FD1F...
Page 228: Pwm Clock Control Register (Pwmckcr)
Section 9 8-Bit PWM Timer (PWMU) 9.3.1 PWM Clock Control Register (PWMCKCR) PWMCKCR selects the PWM clock source. Initial Bit Name Value Description 7, 6 CLK1, CLK0 All 0 Clock Select 1, 0 These bits select the PWM count clock source. CLK1 CLK0 0: Internal clock φ...
Page 229 Section 9 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description CNTMD23B Channel 4 and 5, 12-bit Counter Select 0: Channel 4 and 5 are set to 8-bit count operating mode 1: Channel 4 and 5 are set to 12-bit count operating mode When selecting 12-bit count operating mode, 16-bit count mode must be non-selectable (CNTMD23A =...
Page 230 Section 9 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description PWM2E PWMU2 Output Enable • 8-bit single-pulse/pulse division mode 0: PWMU2 output and counter operation are disabled. 1: PWMU2 output and counter operation are enabled. • 12/16-bit single-pulse mode 0: PWMU2 output and counter operation are disabled.
Page 231: Pwm Mode Control Register C (Pwmmdcr)
Section 9 8-Bit PWM Timer (PWMU) 9.3.3 PWM Mode Control Register C (PWMMDCR) PWMMDCR selects the PWM count mode and operating mode for each channel. Initial Bit Name Value Description CNTMD01B Channel 0 and 1, 12-bit Counter Select 0: Channel 0 and 1 are set to 8-bit count operating mode 1: Channel 0 and 1 are set to 12-bit count operating mode...
Page 232: Pwm Phase Control Register (Pwmpcr)
Section 9 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description PWMSL1 Channel 1 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) PWMSL0 Channel 0 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 9.3.4 PWM Phase Control Register (PWMPCR) PWMPCR selects the PWM count mode and output phase for each channel.
Page 233: Pwm Prescaler Latch Register (Prelat)
Section 9 8-Bit PWM Timer (PWMU) Initial Bit Name Value Description CNTMD45A Channel 4 and 5, 16-bit Counter Select 0: Channel 4 and 5 are set to 8-bit count operating mode 1: Channel 4 and 5 are set to 16-bit count operating mode When selecting 16-bit count operating mode, 12-bit count mode must be non-selectable (CNTMD45B =...
Page 234: Pwm Duty Setting Latch Register (Reglat)
Section 9 8-Bit PWM Timer (PWMU) 9.3.6 PWM Duty Setting Latch Register (REGLAT) REGLAT is a shift register in PWMREG. When one pulse is completed, the data of PWMREG is transferred to PRELAT automatically. This register cannot be accessed by the CPU directly. Table 9.3 Counter Operation of the Channel 0 and 1 CNTMD01A in...
Page 235: Pwm Prescaler Registers 0 To 5 (Pwmpre0 To Pwmpre5)
Section 9 8-Bit PWM Timer (PWMU) Table 9.5 Counter Operation of the Channel 4 and 5 CNTMD45A in CNTMD45B in PWMMPCR PWMOUTCR Counter Operation of the Channel 4 and 5 8-bit counter operation 12-bit counter operation (higher order: channel 5, lower order: channel 4) 16-bit counter operation (higher order: channel 5, lower order: channel 4) Setting prohibited...
Page 236 Section 9 8-Bit PWM Timer (PWMU) 12-Bit Single Pulse Mode When 12-bit single pulse mode is selected, PWMPRE0, PWMPRE2, and PWMPRE4 are valid. The settings of PWMPRE1, PWMPRE3, and PWMPRE5 are invalid. PWM cycle = [4095 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) Resolution, PWM Conversion Period, and Carrier Frequency when φ...
Page 237 Section 9 8-Bit PWM Timer (PWMU) 8-Bit Pulse Division Mode PWM cycle = [16 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) PWM conversion cycle = [256 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) Resolution, PWM Conversion Period, and Carrier Frequency when φ...
Page 238: Pwm Duty Setting Registers 0 To 5 (Pwmreg0 To Pwmreg5)
Section 9 8-Bit PWM Timer (PWMU) 9.3.8 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5) PWMREG are 8-bit readable/writable registers used to set the high period (duty) of the PWM output pulse. The initial value is H'00. 8-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output.
Page 239 Section 9 8-Bit PWM Timer (PWMU) 16-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output. With cascade-connected PWMREG registers, the duty cycle of the PWM output pulse is specified as a value from 0/65535 to 65535/65535.
Page 240: Operation
Section 9 8-Bit PWM Timer (PWMU) Operation The PWMU operates in 8-bit single pulse mode, 12-bit single pulse mode, 16-bit single pulse mode, or 8-bit division pulse mode. 9.4.1 Single-Pulse Mode (8 Bits, 12 Bits, and 16 Bits) Figure 9.2 shows a block diagram of 8-bit single pulse mode. Figure 9.3 shows a block diagram of 12 and 16-bit single pulse mode.
Page 241 Section 9 8-Bit PWM Timer (PWMU) Clock PRELAT0 CNT0 generator Comparator 0 PWMU00 (Output disabled) REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 9.3 Block Diagram of 12 and 16-bit Single Pulse Mode When the PWMnE bit (n = 0 to 5) in PWMOUTCR is set to 1, the PWMU outputs pulses that start with a high level.
Page 242 Section 9 8-Bit PWM Timer (PWMU) The following shows the duty counter value and PWMU output timing. Duty counter H'FF REGLAT H'00 PWMUO Figure 9.5 Duty Counter Value and PWMU Output Timing If the PWMREG value is changed during PWM output, the PWMREG value is loaded into REGLAT when the duty counter overflows (at the beginning of the next PWM cycle).
Page 243 Section 9 8-Bit PWM Timer (PWMU) When the PWMPRE value is changed during PWM output, the PWM cycle changes from the next cycle. When the clock generator counter underflows, the PWMPRE value is loaded into PRELAT. The following shows the PRELAT update timing when the PWMPRE value is changed. Clock generation counter PRELAT PRELAT...
Page 244: Pulse Division Mode
Section 9 8-Bit PWM Timer (PWMU) 9.4.2 Pulse Division Mode In pulse division mode, the higher-order four bits in PWMREG specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The following shows the duty cycle of the basic pulse.
Page 245 Section 9 8-Bit PWM Timer (PWMU) The lower four bits in PWMREG specify the position of pulses added to the 16 basic pulses. The additional pulse adds a high period (when PHnS = 0) at the resolution width before the rising edge of the basic pulse.
Page 246 Section 9 8-Bit PWM Timer (PWMU) Example of Setting 1 conversion period PWMREG setting Basic Additional example waveform pulses Duty cycle H'7F 127/256 112 pulses 15 pulses H'80 128/256 128 pulses 0 pulse H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses...
Page 247: Usage Note
Section 9 8-Bit PWM Timer (PWMU) Usage Note 9.5.1 Setting Module Stop Mode The module stop control register can be used to enable or disable PWMU operation. The default setting disables PWMU operation. Clearing the module stop mode enables registers to be accessed.
Page 248 Section 9 8-Bit PWM Timer (PWMU) Rev. 1.00 May 09, 2008 Page 222 of 954 REJ09B0462-0100...
Page 249: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
Page 250 Section 10 16-Bit Timer Pulse Unit (TPU) Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 Internal data bus φ/256 φ/1024 A/D converter convertion External clock: TCLKA start signal TCLKB TCLKC TCLKD Input/output pins Interrupt request signals Channel 0: TGI0A Channel 0: TIOCA0 TGI0B TIOCB0...
Page 251 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/256 φ/1024 TCLKA TCLKB TCLKA TCLKA TCLKC TCLKB TCLKB TCLKD TCLKC...
Page 252 Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 A/D converter trigger TGRA_0 compare TGRA_1 compare TGRA_2 compare match or input capture match or input capture match or input capture Interrupt sources 5 sources 4 sources 4 sources •...
Page 253: Input/Output Pins
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.2 Pin Configuration Channel Pin Name Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input...
Page 254: Register Descriptions
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. Table 10.3 Register Configuration Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 0 Timer control register_0 TCR_0 H'00 H'FE50 Timer mode register_0 TMDR_0 H'C0 H'FE51...
Page 255: Timer Control Register (Tcr)
Section 10 16-Bit Timer Pulse Unit (TPU) Initial Data Bus Channel Register Name Abbreviation R/W Value Address Width Channel 2 Timer general register A_2 TGRA_2 H'FFFF H'FE78 Timer general register B_2 TGRB_2 H'FFFF H'FE7A 16 Common Timer start register TSTR H'00 H'FEB0 8 Timer synchro register...
Page 256 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.4 CCLR2 to CCLR0 (channel 0) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing...
Page 257 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.6 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 258 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.8 TPSC2 to TPSC0 (channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 259: Timer Mode Register (Tmdr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped.
Page 260 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.9 MD3 to MD0 Bit 3 Bit2 Bit 1 Bit 0 Description MD3* MD2* Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 261: Timer I/O Control Register (Tior)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting.
Page 262 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.10 TIORH_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 263 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.11 TIORH_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 264 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 TIORL_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled Compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 265 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 TIORL_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 1 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 266 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 TIOR_1 (channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 267 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIOR_1 (channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 268 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIOR_2 (channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 269 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIOR_2 (channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match...
Page 270: Timer Interrupt Enable Register (Tier)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Initial Bit Name value Description TTGE A/D Conversion Start Request Enable...
Page 271 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 272: Timer Status Register (Tsr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Initial Bit Name value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2.
Page 273 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Page 274 Section 10 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 275: Timer Counter (Tcnt)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units;...
Page 276: Timer Synchro Register (Tsyr)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to Initial Bit Name value...
Page 277: Interface To Bus Master
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units;...
Page 278 Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus Module master Bus interface data bus Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus Module master...
Page 279: Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of free- running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Page 280 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 281 Section 10 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software activation Figure 10.8 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 282 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B.
Page 283 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure.
Page 284 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 285: Synchronous Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 286 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 287: Buffer Operation
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 288 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure Figure 10.18 shows an example of the buffer operation setting procedure. Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits Select TGR function BFA and BFB in TMDR.
Page 289 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 290 Section 10 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 291: Pwm Modes
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty.
Page 292 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 TGRA_2 TIOCA2 TIOCA2...
Page 293 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value.
Page 294 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA TCNT value Output does not change when cycle register and duty register TGRB rewritten compare matches occur simultaneously...
Page 295: Phase Counting Mode
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 296 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.21 summarizes the TCNT up/down-count conditions.
Page 297 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count...
Page 298 Section 10 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count...
Page 299 Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.24 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 300: Interrupts
Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 Interrupts 10.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Page 301: A/D Converter Activation
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 302: Operation Timing
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Operation Timing 10.7.1 Input/Output Timing TCNT Count Timing Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT...
Page 303 Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 304 Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. φ...
Page 305 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 10.36 and 10.37 show the timing in buffer operation. φ TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal N + 1...
Page 306: Interrupt Signal Timing
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ...
Page 307 Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 308 Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the timing for status flag clearing by the CPU. TSR write cycle φ...
Page 309: Usage Notes
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 Usage Notes 10.8.1 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 310: Conflict Between Tcnt Write And Clear Operations
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.3 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case. TCNT write cycle φ...
Page 311: Conflict Between Tgr Write And Compare Match
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.5 Conflict between TGR Write and Compare Match If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written.
Page 312: Conflict Between Tgr Read And Input Capture
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.7 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.48 shows the timing in this case. TGR read cycle φ...
Page 313: Conflict Between Buffer Register Write And Input Capture
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.9 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.50 shows the timing in this case.
Page 314: 10.8.10 Conflict Between Overflow/Underflow And Counter Clearing
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 315: 10.8.12 Multiplexing Of I/O Pins
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.12 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 316 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 May 09, 2008 Page 290 of 954 REJ09B0462-0100...
Page 317: Section 11 16-Bit Cycle Measurement Timer (Tcm)
Section 11 16-Bit Cycle Measurement Timer (TCM) Section 11 16-Bit Cycle Measurement Timer (TCM) This LSI has three channels on-chip 16-bit cycle measurement timers (TCM). Each TCM has a 16-bit counter that provides the basis for measuring the periods of input waveforms. 11.1 Features •...
Page 318 Section 11 16-Bit Cycle Measurement Timer (TCM) Figure 11.1 is a block diagram of the TCM. External clock Internal clock φ/2, φ/8, φ/16, φ/32 TCMCKI φ/64, φ/128, φ/256 Clock selection Overflow TCMCNT Clear Control Compare matrch logic Comparator TCMMCI Cycle upper limit overflow Cycle lower limit underflow TCMMLCM TCMMINCM...
Page 319: Input/Output Pins
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.2 Input/Output Pins Table 11.1 lists the input and output pins for the TCMs. Table 11.1 Pin Configuration Channel Pin Name Function TCMCKI0 Input External counter clock input (TCMMCI0) Cycle measurement control input TCMCYI0 Input External event input...
Page 320: Register Descriptions
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3 Register Descriptions The TCMs have the following registers. Table 11.2 Register Configuration Initial Data Bus Channel Register Name Abbreviation Value Address Width Channel 0 TCM timer counter_0 TCMCNT_0 R/W H'0000 H'FBC0 TCM cycle upper limit register_0 TCMMLCM_0 R/W H'FFFF H'FBC2 TCM cycle lower limit register_0 TCMMINCM_0 R/W H'0000 H'FBCC...
Page 321: Tcm Timer Counter (Tcmcnt)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.1 TCM Timer Counter (TCMCNT) TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this case, the rising or falling edge is selected by CKSEG in TCMCR.
Page 322: Tcm Cycle Lower Limit Register (Tcmmincm)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) TCMMINCM is a 16-bit readable/writable register. TCMMINCM is available as a cycle lower limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in cycle measurement mode).
Page 323: Tcm Status Register (Tcmcsr)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.6 TCM Status Register (TCMCSR) TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources. Initial Bit Name Value Description R/(W)* Timer Overflow This flag indicates that the TCMCNT has overflowed. [Setting condition] Overflow of TCMCNT (change in value from H'FFFF to H'0000)
Page 324 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description ICPF R/(W)* Input Capture Generation Timer mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on generation of an input capture signal. This flag is set when the input capture signal is generated, i.e.
Page 325: Tcm Control Register (Tcmcr)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.7 TCM Control Register (TCMCR) TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter start, and counter clock, and controls operation mode. Initial Bit Name Value Description Counter Start In timer mode, setting this bit to 1 starts counting by TCMCNT;...
Page 326 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description IEDG Input Edge Select In timer mode, selects the falling or rising edge of the TCMCYI input for use in input capture, in combination with the value of the POCTL bit. In cycle measurement mode, selects the falling or rising edge of the TCMCYI input for use in measurement, in combination with the value of the POCTL bit.
Page 327: Tcm Interrupt Enable Register (Tcmier)
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.8 TCM Interrupt Enable Register (TCMIER) TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests. Initial Bit Name Value Description OVIE Counter Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the OVF flag in TCMCSR to 1.
Page 328 Section 11 16-Bit Cycle Measurement Timer (TCM) Initial Bit Name Value Description MINUDIE Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of the TUDI interrupt requests when the MINUDF flag in TCMCSR is set to 1. 0: Disable interrupt requests by MINUDF 1: Enable interrupt requests by MINUDF CMMS Cycle Measurement Mode Selection...
Page 329: Operation
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.4 Operation The TCM operates in timer mode or cycle measurement mode. TCM is in timer mode after a reset. 11.4.1 Timer Mode When the TCMMDS bit in TCMCR is cleared to 0, TCM operates in timer mode. Counter Operation TCMCNT operates as a free running counter in timer mode.
Page 330 Section 11 16-Bit Cycle Measurement Timer (TCM) Input Capture The value in TCMCNT is transferred to TCMICR by detecting input edge of TCMCYI pin in timer mode. At this time, the ICPF flag in TCMCSR is set. Detection of rising or falling edges is selectable with the setting of the IEDG bit in TCMCR.
Page 331: Cycle Measurement Mode
Section 11 16-Bit Cycle Measurement Timer (TCM) CMF Set Timing when a Compare Match occurs The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM match in timer mode. Therefore, a compare match signal is not generated until a further cycle of the TCMCNT input clock is generated after a match between the values in TCMCNT and TCMMLCM.
Page 332 Section 11 16-Bit Cycle Measurement Timer (TCM) Measuring a Cycle In cycle measurement mode, one cycle of the input waveform for TCM form one measurement cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000. After that, set an upper or lower limit on the measurement cycle in the TCMMLCM/TCMMINCM register.
Page 333 Section 11 16-Bit Cycle Measurement Timer (TCM) When the CMMS bit in TCMIER is set to 1, cycle measurement is performed only while the TCMMCI signal is high (MCICTL in TCMCSR is 1). Figure 11.9 shows an example of timing in cycle measurement when the CMMS bit is set to 1.
Page 334 Section 11 16-Bit Cycle Measurement Timer (TCM) Cycle measurement stops if MAXOVF/MINUDF is set to 1 while the CPSPE bit in TCMCR is set to 1. Subsequently clearing MAXOVF/MINUDF to 0 restarts cycle measurement. In this case, the external event can be considered to have stopped if a timer overflow is generated before detection of the first edge.
Page 335 Section 11 16-Bit Cycle Measurement Timer (TCM) Example of Settings for Cycle Measurement Mode Figure 11.12 shows an example of the flow when cycle measurement mode is to be used. Start Initialization Set timer mode. Set TCMMDS to 0 Stop TCMCNT and initialize to H'0000. Set CST (TCMCR) to 0 Set an upper limit on the measurement period.
Page 336: Interrupt Sources
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.5 Interrupt Sources TCM has five interrupt sources: TICI, TCMI, TOVMI, TUDI, and TOVI. Each interrupt source is either enabled or disabled by the corresponding interrupt enable bit in TCMIER and independently transferred to the interrupt controller. Since a single vector address is allocated for each type of interrupt source from all channels, the flags must be used to discriminate between the sources.
Page 337: Usage Notes
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6 Usage Notes 11.6.1 Conflict between TCMCNT Write and Count-Up Operation When a conflict between TCMCNT write and count-up operation occurs in the second half of the TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority. Figure 11.13 shows the timing of this conflict.
Page 338: Conflict Between Tcmicr Read And Input Capture
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.3 Conflict between TCMICR Read and Input Capture When operation is in timer mode and the corresponding input capture signal is detected during reading of TCMICR, the input capture signal is delayed by one system clock (φ). Figure 11.15 shows the timing of this conflict.
Page 339: Conflict Between Edge Detection In Cycle Measurement Mode And Clearing Of Tcmmds Bit In Tcmcr
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of TCMMDS Bit in TCMCR If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of the selected edge will cause the timer to continue to operate in cycle measurement mode.
Page 340 Section 11 16-Bit Cycle Measurement Timer (TCM) Rev. 1.00 May 09, 2008 Page 314 of 954 REJ09B0462-0100...
Page 341: Section 12 8-Bit Timer (Tmr)
Section 12 8-Bit Timer (TMR) Section 12 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 342 Section 12 8-Bit Timer (TMR) Figures 12.1 and 12.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. External clock sources Internal clock sources TMR_0 TMI0 (TMCI0) φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024 TMI1 (TMCI1) TMR_1 φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048 Clock 1...
Page 343 Section 12 8-Bit Timer (TMR) Internal clock sources External clock sources TMR_X TMIY (TMCIY) φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192 TMIX (TMCIX) TMR_Y φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384 Clock X Clock Y Clock selection TCORA_Y TCORA_X Compare-match AX Comparator A_Y Comparator A_X Compare-match AY Overflow X...
Page 344: Input/Output Pins
Section 12 8-Bit Timer (TMR) 12.2 Input/Output Pins Table 12.1 summarizes the input and output pins of the TMR. Table 12.1 Pin Configuration Channel Pin Name Function TMR_0 TMO0 Output Output controlled by compare-match TMI0 Input External clock input/external reset input for the (TMCI0/TMRI0) counter TMR_1...
Page 345: Register Descriptions
Section 12 8-Bit Timer (TMR) 12.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Table 12.2 Register Configuration Data Initial Channel Register Name Abbreviation R/W Value Address Width...
Page 346 Section 12 8-Bit Timer (TMR) Data Initial Channel Register Name Abbreviation R/W Value Address Width Channel X Timer counter_X TCNT_X H'00 H'FFF4 Time constant register A_X TCORA_X H'FF H'FFF6 Time constant register B_X TCORB_X H'FF H'FFF7 Timer control register_X TCR_X H'00 H'FFF0 Timer control/status register_X TCSR_X...
Page 347: Timer Counter (Tcnt)
Section 12 8-Bit Timer (TMR) 12.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_X and TCNT_Y) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal.
Page 348: Timer Control Register (Tcr)
Section 12 8-Bit Timer (TMR) 12.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Initial Bit Name Value Description CMIEB Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Page 349 Section 12 8-Bit Timer (TMR) Table 12.3 Clock Input to TCNT and Count Condition (1) STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description TMR_0 — — Disables clock input — Increments at falling edge of internal clock φ/8 — Increments at falling edge of internal clock φ/2 —...
Page 350 Section 12 8-Bit Timer (TMR) STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Common — — Increments at rising edge of external clock — — Increments at falling edge of external clock — — Increments at both rising and falling edges of external clock Note: If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock...
Page 351 Section 12 8-Bit Timer (TMR) TCRXY Channel CKS2 Description CKS1 CKS0 CKSX CKSY TMR_X — Disables clock input Increments at φ — Increments at φ/2 — Increments at φ/4 — — Disables clock input — Disables clock input Increments at φ/2048 —...
Page 352: Timer Control/Status Register (Tcsr)
Section 12 8-Bit Timer (TMR) 12.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. • TCSR_0 Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA...
Page 353 Section 12 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 1 and 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 354 Section 12 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 3 and 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Output Select 1 and 0...
Page 355 Section 12 8-Bit Timer (TMR) Initial Bit Name Value Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF ICIE Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1.
Page 356 Section 12 8-Bit Timer (TMR) • TCSR_X Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA R/(W)* Compare-Match Flag A [Setting condition]...
Page 357: Time Constant Register C (Tcorc)
Section 12 8-Bit Timer (TMR) Initial Bit Name Value Description Output Select 1 and 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note:...
Page 358: Timer Connection Register I (Tconri)
Section 12 8-Bit Timer (TMR) 12.3.8 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Initial Bit Name Value Description 7 to 5 — All 0 Reserved The initial value should not be changed. ICST Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF).
Page 359: Timer Xy Control Register (Tcrxy)
Section 12 8-Bit Timer (TMR) Table 12.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TCR_X TCSR_X TICRR TICRF TCNT TCORC TCORA_X TCORB_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TCR_Y...
Page 360: Operation
Section 12 8-Bit Timer (TMR) 12.4 Operation 12.4.1 Pulse Output Figure 12.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA.
Page 361: Operation Timing
Section 12 8-Bit Timer (TMR) 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges.
Page 362: Timing Of Cmfa And Cmfb Setting At Compare-Match
Section 12 8-Bit Timer (TMR) 12.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated.
Page 363: Timing Of Counter Clear At Compare-Match
Section 12 8-Bit Timer (TMR) 12.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a compare-match.
Page 364: Timing Of Overflow Flag (Ovf) Setting
Section 12 8-Bit Timer (TMR) 12.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 12.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00...
Page 365: Tmr_0 And Tmr_1 Cascaded Connection
Section 12 8-Bit Timer (TMR) 12.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available.
Page 366: Tmr_Y And Tmr_X Cascaded Connection
Section 12 8-Bit Timer (TMR) 12.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY.
Page 367: Input Capture Operation
Section 12 8-Bit Timer (TMR) 12.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF.
Page 368 Section 12 8-Bit Timer (TMR) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 12.5. Table 12.5 Input Capture Signal Selection TCONRI Bit 4...
Page 369: Interrupt Sources
Section 12 8-Bit Timer (TMR) 12.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 12.6 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR.
Page 370: Usage Notes
Section 12 8-Bit Timer (TMR) 12.9 Usage Notes 12.9.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T state of a TCNT write cycle as shown in figure 12.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU φ...
Page 371: Conflict Between Tcor Write And Compare-Match
Section 12 8-Bit Timer (TMR) 12.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T state of a TCOR write cycle as shown in figure 12.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
Page 372: Switching Of Internal Clocks And Tcnt Operation
Section 12 8-Bit Timer (TMR) 12.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation.
Page 373 Section 12 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock switching from high Clock before switchover to low level* Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Clock switching from high Clock before...
Page 374: Mode Setting With Cascaded Connection
Section 12 8-Bit Timer (TMR) 12.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating.
Page 375: Section 13 Watchdog Timer (Wdt)
Section 13 Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
Page 376 Section 13 Watchdog Timer (WDT) φ/2 φ/64 WOVI0 φ/128 Interrupt (Interrupt request signal) φ/512 control Clock Overflow Clock φ/2048 selection Internal NMI φ/8192 Reset (Interrupt request signal* φ/32768 control φ/131072 Internal clock Internal reset signal* TCNT_0 TCSR_0 interface Module bus WDT_0 φ/2 φSUB/2...
Page 377: Input/Output Pins
Section 13 Watchdog Timer (WDT) 13.2 Input/Output Pins The WDT has the pins listed in table 13.1. Table 13.1 Pin Configuration Name Pin Name Function External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1 prescaler counter 13.3 Register Descriptions The WDT has the following registers.
Page 378: Timer Counter (Tcnt)
Section 13 Watchdog Timer (WDT) 13.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 13.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. •...
Page 379 Section 13 Watchdog Timer (WDT) Initial Bit Name Value Description  R/(W) Reserved The initial value should not be changed. RST/NMI Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested CKS2 Clock Select 2 to 0...
Page 380 Section 13 Watchdog Timer (WDT) • TCSR_1 Initial Bit Name Value Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 381 Section 13 Watchdog Timer (WDT) Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz and φSUB = 32.768 CKS0 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 25.6 µs) 001: φ/64 (frequency: 819.2 µs)
Page 382: Operation
Section 13 Watchdog Timer (WDT) 13.4 Operation 13.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated.
Page 383: Interval Timer Mode
Section 13 Watchdog Timer (WDT) 13.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 13.3. Therefore, an interrupt can be generated at intervals.
Page 384: Interrupt Sources
Section 13 Watchdog Timer (WDT) 13.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
Page 385: Usage Notes
Section 13 Watchdog Timer (WDT) 13.6 Usage Notes 13.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below.
Page 386: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 13 Watchdog Timer (WDT) 13.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.6 shows this operation. TCNT write cycle φ...
Page 387: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) Section 14 Serial Communication Interface (SCI) This LSI has a serial communication interface (SCI) channel. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 388 Section 14 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity error during reception. • Data can be automatically re-transmitted on detection of an error signal during transmission. •...
Page 389: Input/Output Pins
Section 14 Serial Communication Interface (SCI) 14.2 Input/Output Pins Table 14.1 shows the input/output pins for each SCI channel. Table 14.1 Pin Configuration Channel Pin Name* Input/Output Function SCK1 Input/Output Channel 1 clock input/output RxD1 Input Channel 1 receive data input TxD1 Output Channel 1 transmit data output...
Page 390: Receive Shift Register (Rsr)
Section 14 Serial Communication Interface (SCI) 14.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 391: Serial Mode Register (Smr)
Section 14 Serial Communication Interface (SCI) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. The CPU can always read SMR.
Page 392 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description STOP Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 393 Section 14 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu* from the start and the clock output control function is appended.
Page 394 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description CKS1 Clock Select 1 and 0 CKS0 These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting...
Page 395: Serial Control Register (Scr)
Section 14 Serial Communication Interface (SCI) 14.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 14.8, Interrupt Sources.
Page 396 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description CKE1 Clock Enable 1 and 0 CKE0 These bits select the clock source and SCK pin function. • Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency...
Page 397 Section 14 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Page 398: Serial Status Register (Ssr)
Section 14 Serial Communication Interface (SCI) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Page 399 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
Page 400 Section 14 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Name Initial Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and TDR can be written to.
Page 401 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 TEND Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR.
Page 402: Smart Card Mode Register (Scmr)
Section 14 Serial Communication Interface (SCI) 14.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Name Initial Value Description  7 to 4 All 1 Reserved These bits are always read as 1 and cannot be modified.
Page 403: Bit Rate Register (Brr)
Section 14 Serial Communication Interface (SCI) 14.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.3 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 404 Section 14 Serial Communication Interface (SCI) Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 9.8304 Bit Rate Error Error Error Error (bit/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16...
Page 405 Section 14 Serial Communication Interface (SCI) Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency f (MHz) 17.2032 19.6608 Bit Rate Error Error Error Error Error (bit/s) 0.48 –0.12 3 0.31 3 88 –0.25 3 110 –0.02 223 0.00 0.16...
Page 406 Section 14 Serial Communication Interface (SCI) Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) External Input Maximum Bit External Input Maximum Bit φ (MHz) φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 2.0000 125000 14.7456 3.6864 230400 9.8304...
Page 407 Section 14 Serial Communication Interface (SCI) Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Rate (bit/s)           2.5k 100k 250k 500k 2.5M [Legend] Blank: Setting prohibited. ...
Page 408 Section 14 Serial Communication Interface (SCI) Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) External Input Maximum Bit External Input Maximum Bit φ (MHz) φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 1.3333 1333333.3 2.6667 2666666.7 1.6667...
Page 409: Operation In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 410: Data Transfer Format
Section 14 Serial Communication Interface (SCI) 14.4.1 Data Transfer Format Table 14.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 14.5, Multiprocessor Communication Function.
Page 411: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 412: Clock
Section 14 Serial Communication Interface (SCI) 14.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 413: Sci Initialization (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 14.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 414: Serial Data Transmission (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.4.5 Serial Data Transmission (Asynchronous Mode) Figure 14.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 415 Section 14 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 416: Serial Data Reception (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.4.6 Serial Data Reception (Asynchronous Mode) Figure 14.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 417 Section 14 Serial Communication Interface (SCI) Table 14.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 418 Section 14 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 419 Section 14 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 420: Multiprocessor Communication Function
Section 14 Serial Communication Interface (SCI) 14.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 421 Section 14 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle =...
Page 422: Multiprocessor Serial Data Transmission
Section 14 Serial Communication Interface (SCI) 14.5.1 Multiprocessor Serial Data Transmission Figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 423: Multiprocessor Serial Data Reception
Section 14 Serial Communication Interface (SCI) 14.5.2 Multiprocessor Serial Data Reception Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 424 Section 14 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] ID reception cycle: Set MPIE bit in SCR to 1 Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR [3] SCI status check, ID reception and comparison:...
Page 425 Section 14 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 426: Operation In Clocked Synchronous Mode
Section 14 Serial Communication Interface (SCI) 14.6 Operation in Clocked Synchronous Mode Figure 14.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 427: Sci Initialization (Clocked Synchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 14.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 428: Serial Data Transmission (Clocked Synchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 429 Section 14 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Data written to TDR and TXI interrupt request TEI interrupt request generated TDRE flag cleared to 0 in generated...
Page 430: Serial Data Reception (Clocked Synchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 431 Section 14 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 432: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 14 Serial Communication Interface (SCI) 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 433 Section 14 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin Start transmission/reception is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag...
Page 434: Smart Card Interface Description
Section 14 Serial Communication Interface (SCI) 14.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 14.7.1 Sample Connection Figure 14.21 shows a sample connection between the smart card and this LSI.
Page 435: Data Format (Except In Block Transfer Mode)
Section 14 Serial Communication Interface (SCI) 14.7.2 Data Format (Except in Block Transfer Mode) Figure 14.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
Page 436: Block Transfer Mode
Section 14 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 14.23. Therefore, data in the start character in the figure is H'3B.
Page 437: Receive Data Sampling Timing And Reception Margin
Section 14 Serial Communication Interface (SCI) 14.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 438: Initialization
Section 14 Serial Communication Interface (SCI) 14.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2.
Page 439 Section 14 Serial Communication Interface (SCI) 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1.
Page 440 Section 14 Serial Communication Interface (SCI) Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 14.27. I/O data Guard time (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 [Legend]...
Page 441 Section 14 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0 Error processing TEND = 1 Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted ERS = 0 Error processing TEND = 1 Clear TE bit in SCR to 0 Figure 14.28 Sample Transmission Flowchart Rev.
Page 442: Serial Data Reception (Except In Block Transfer Mode)
Section 14 Serial Communication Interface (SCI) 14.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 14.29 shows the data re-transfer operation during reception. 1.
Page 443 Section 14 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0 Error processing RDRF = 1 Read data from RDR and clear RDRF flag in SSR to 0 All data received Clear RE bit in SCR to 0 Figure 14.30 Sample Reception Flowchart Rev.
Page 444: Clock Output Control
Section 14 Serial Communication Interface (SCI) 14.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 14.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
Page 445 Section 14 Serial Communication Interface (SCI) At Transition from Smart Card Interface Mode to Software Standby Mode 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2.
Page 446: Interrupt Sources
Section 14 Serial Communication Interface (SCI) 14.8 Interrupt Sources 14.8.1 Interrupts in Normal Serial Communication Interface Mode Table 14.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 447: Interrupts In Smart Card Interface Mode
Section 14 Serial Communication Interface (SCI) 14.8.2 Interrupts in Smart Card Interface Mode Table 14.13 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 14.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag...
Page 448: Usage Notes
Section 14 Serial Communication Interface (SCI) 14.9 Usage Notes 14.9.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes.
Page 449: Sci Operations During Mode Transitions
Section 14 Serial Communication Interface (SCI) 14.9.6 SCI Operations during Mode Transitions Transmission Before making the transition to module stop or software standby, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again.
Page 450 Section 14 Serial Communication Interface (SCI) Transition to Software standby software standby Transmission start Transmission end mode cancelled mode TE bit Port input/output output pin Port High output Start Stop Port input/output High output output pin input/output SCI TxD output Port Port TxD output...
Page 451 Section 14 Serial Communication Interface (SCI) Reception Before making the transition to module stop, software standby or watch mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid.
Page 452: Notes On Switching From Sck Pins To Port Pins
Section 14 Serial Communication Interface (SCI) 14.9.7 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 14.37. Low pulse of half a cycle SCK/Port 1.
Page 453: Note On Writing To Registers In Transmission, Reception, And Simultaneous Transmission And Reception
Section 14 Serial Communication Interface (SCI) 14.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception After 1 is set to the TE and RE bits in SCR to start transmission, reception, and simultaneous transmission and reception, do not write to SMR, SCR, BRR, and SDCR. Also, do not overwrite the same value as the register value.
Page 454 Section 14 Serial Communication Interface (SCI) Rev. 1.00 May 09, 2008 Page 428 of 954 REJ09B0462-0100...
Page 455: Section 15 Cir Interface
Section 15 CIR Interface Section 15 CIR Interface This LSI incorporates a custom infra-red interface (CIR). The CIR has various functions for receiving the IR signal in NEC format. 15.1 Features • Supports reception of the IR signal in NEC format •...
Page 456 Section 15 CIR Interface Module data bus HHMAX HHMIN CCR1 CIRRDR φ HLMAX HLMIN 0 to 7 CCR2 (8-byte φ/2 DT0MAX DT0MIN CSTR FIFO) Baud rate generator φ/4 DT1MAX DT1MIN φ CEIR RMAX RMIN CIRI 4-stage filter Reception control Sampling clock RENDI OVEI REPI...
Page 457: Input Pins
Section 15 CIR Interface 15.2 Input Pins Table 15.1 shows the input pin of the CIR. Table 15.1 Pin Configuration Pin Name Symbol Function CIR input pin CIRI Input CIR receive data input pin 15.3 Register Description Table 15.2 shows the CIR register configuration. Table 15.2 List of Register Addresses Register Name Abbreviation...
Page 458: Receive Control Register 1 (Ccr1)
Section 15 CIR Interface Register Name Abbreviation Initial Value Address Repeat header minimum low-level period RMIN H'00 H'FA50 register Repeat header maximum low-level period RMAX H'00 H'FA51 register Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0. 2.
Page 459: Receive Control Register 2 (Ccr2)
Section 15 CIR Interface Initial Bit Name Value Description REPRCVE Receive Enable after Repeat Detection Enables/disables the CIR reception after a repeat detection. 0: The CIR reception is disabled by a repeat detection. 1: The CIR reception is enabled by a repeat detection ...
Page 460: Receive Status Register (Cstr)
Section 15 CIR Interface 15.3.3 Receive Status Register (CSTR) CSTR indicates the data reception state of the CIR. Initial Bit Name Value Description CIRBUSY CIR Busy Flag Indicates the data receive state of the CIR. [Setting condition] When the CIR starts data reception. [Clearing condition] When the CIR has finished data reception.
Page 461 Section 15 CIR Interface Initial Bit Name Value Description REND R/W* Reception End Flag [Setting condition] When the CIR has finished data reception. (When a stop is detected.) [Clearing condition] When writing 0 after reading REND = 1. R/W* Abort Flag An internal reset is generated when an abort (transfer format) is detected.
Page 462: Interrupt Enable Register (Ceir)
Section 15 CIR Interface 15.3.4 Interrupt Enable Register (CEIR) CEIR consists of the bits that enable/disable various interrupts. Initial Bit Name Value Description  7, 6 All 0 Reserved The initial value should not be changed. REPIE Repeat Detection Interrupt Enable 0: REPI interrupt request is disabled.
Page 463: Bit Rate Register (Brr)
Section 15 CIR Interface 15.3.5 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate for the CIR reception is determined by a combination of the setting value in BRR and the CLK1 and CLK0 bits in CCR1.
Page 464: Receive Data Register 0 To 7 (Cirrdr0 To Cirrdr7)
Section 15 CIR Interface 15.3.6 Receive Data Register 0 to 7 (CIRRDR0 to CIRRDR7) CIRRDR0 to CIRRDR7 are an 8-byte register that stores receive data, totaling to 8 bytes. CIRRDR0 to CIRRDR7 share one byte of the register address. A receive data in CIRRDR should be read after the CIR has finished data reception (CIRBUSY = 0).
Page 465 Section 15 CIR Interface • HHMAX Initial Bit Name Value Description FLT1 Number of Stages of Noise Canceler Circuit Select FLT0 00: The noise canceler circuit consists of one stage 01: The noise canceler circuit consists of two stages 10: The noise canceler circuit consists of three stages 11: The noise canceler circuit consists of four stages FLTE...
Page 466: Header Minimum/Maximum Low-Level Period Register (Hlmin/Hlmax)
Section 15 CIR Interface 15.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX) HLMIN and HLMAX specify the minimum and maximum low-level period for a header. • HLMIN Initial Bit Name Value Description 7 to 0 HLMIN7 to H'00 Specifies the minimum low-level period for a header. HLMIN0 •...
Page 467: Data Level 0 Minimum/Maximum Period Register (Dt0Min/Dt0Max)
Section 15 CIR Interface 15.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) DT0MIN and DT0MAX specify the minimum and maximum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. • DT0MIN Initial Bit Name Value Description 7 to 0...
Page 468: Operation
Section 15 CIR Interface 15.4 Operation The communication protocol of the NEC format is shown in figure 15.2. In the NEC format, data consists of a header part, an address part, a command part, and a stop part. The TFM bits in CCR2 can select which data bytes to be stored in CIRRDR: four bytes of the address, address, command, and command, or two bytes of the address and command.
Page 469 Section 15 CIR Interface Stop When a low-level period of 9 ms or more is detected after the reception of a command, the CIR stops data reception. This is not defined in the NEC format. Command Stop CIRI A = 9.0 ms C = 0.56 ms D = 1.78 ms [Legend]...
Page 470: Determination Of Signal Type By Low/High-Level Period
Section 15 CIR Interface 15.4.1 Determination of Signal Type by Low/High-Level Period The signal type is determined by low/high-level period that is specified in the HHMIN, HHMAX, HLMIN, HLMAX, DT1MIN, DT1MAX, DT0MIN, DT0MAX, RMIN, and RMAX registers. Each register is used to specify the period described in table 15.4. The symbols in table 15.4 correspond to the ones used in the figure 15.3 to figure 15.5.
Page 471 Section 15 CIR Interface Table 15.4 An Example of Signal Type Determination Register Setting Prescribed Register Setting Setting Time Name Value Time (Error: 30%) Notes Description Symbol Minimum high-level period HHMIN H'079 6.34 ms 6.3 ms HHMIN9 to for a header or repeat HHMIN0 header and minimum low- level period for a stop...
Page 472: Operation Of Fifo Register
Section 15 CIR Interface 15.4.2 Operation of FIFO Register A FIFO structure provides first-in first-out operation. Operation of the FIFO when it receives data three times (byte 0, byte 1, and byte 2 in order) and is then read three times is as shown below. Operation for first reception Operation for data reception of data...
Page 473: Operation In Watch Mode
Section 15 CIR Interface In case of reading more bytes than the number that has been received, (number of received bytes + 1) of data are always read out from the FIFO. Reception of more than 8 bytes by the FIFO structure for this CIR module leads to an overrun. When an overrun occurs, only values up to the 8th byte to have been received are read out in response to the reading of more than 8 bytes.
Page 474: Noise Canceler Circuit
Section 15 CIR Interface 15.5 Noise Canceler Circuit The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise canceler circuit, and select the division ratio for generating the noise canceler circuit clock, respectively.
Page 475 Section 15 CIR Interface Table 15.5 shows sample settings for the noise canceler circuit. Table 15.5 Sample Settings for Noise Canceler Circuit CLK1 and FLTCK1 and Number of Stages Width of CLK0 FLTCK0 Sampling of Noise Canceler Noise φ Setting Setting Setting Clock...
Page 476: Reset Conditions
Section 15 CIR Interface CLK1 and Number of Stages Width of CLK0 FLTCK Sampling of Noise Canceler Noise φ Setting Setting Setting Clock Circuit Cancellation  φ 31.3 µs 31.3 µs H'00 Not divided 62.5 µs 93.8 µs 125 µs 156 µs 62.5 µs 62.5 µs...
Page 477: Interrupt Sources
Section 15 CIR Interface 15.7 Interrupt Sources The CIR has six interrupt source flags for this LSI. Setting the corresponding enable bit to 1 enables the relevant interrupt request to be issued. Since the six interrupt requests are allocated to one vector address, it is necessary for the CPU to check the interrupt request flags in order to determine which interrupt source has caused the interrupt to be requested.
Page 478: Usage Note
Section 15 CIR Interface 15.8 Usage Note CIR Register Setting Before starting the CIR reception, set the CIR by following the flow shown in figure 15.7. Start of setting Clear MSTPA3 bit in MSTPCRA to 0. Set CPHS bit in CCR1. Set each register.
Page 479 Section 15 CIR Interface Overrun Operation with the NEC Format (2 Bytes are Used) When the reception signal format select bits (bits TFM1 and TFM0 in CCR2) are set to the NEC format (2 bytes are used), the OVRF bit in CSTR is set to indicate the overrun on the reception of the 8th byte by the receive data register.
Page 480 Section 15 CIR Interface Rev. 1.00 May 09, 2008 Page 454 of 954 REJ09B0462-0100...
Page 481: Section 16 Serial Communication Interface With Fifo (Scif)
Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that supports asynchronous serial communication. The SCIF enables asynchronous serial communication with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART).
Page 482 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 shows a block diagram of the SCIF. FIER PB2/RI FIIR PB3/DCD FFCR Modem PB4/DSR FLCR controller PB5/DTR FMCR PB6/CTS FLSR PB7/RTS FMSR FSCR FTHR interface Transmit FIFO (16 bytes) P50/FTxD FTSR Transmission Register...
Page 483: Input/Output Pins
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2 Input/Output Pins Table 16.1 lists the SCIF input/output pins. Table 16.1 Pin Configuration Pin Name Port Input/Output Function FTxD Output Transmit data output FRxD Input Receive data input Input Ring indicator input Input Data carrier detect input Input...
Page 484: Register Descriptions
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3 Register Descriptions The SCIF has the following registers. The register configuration of the SCIF is shown below. Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details, see table 16.3.
Page 485: Receive Shift Register (Frsr)
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.3 Register Access SCIFE Bit in HICR5 Bit 3 in MSTPCRB SCIFCR H8S CPU Access disabled H8S CPU Access disabled access* access* Other than SCIFCR H8S CPU Access disabled LPC access* LPC access* access* Notes: 1.
Page 486: Transmitter Shift Register (Ftsr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.3 Transmitter Shift Register (FTSR) FTSR is a register that converts parallel data to serial data and then transmits the serial data from the FTxD pin. When one frame transmission of serial data is completed, the next data is transferred from FTHR.
Page 487: Interrupt Enable Register (Fier)
Section 16 Serial Communication Interface with FIFO (SCIF) • FDLL Bit Name Initial Value Description 7 to 0 Bit 7 to All 0 Lower 8 bits of divisor latch bit 0 Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value) 16.3.6 Interrupt Enable Register (FIER) FIER is a register that enables or disables interrupts.
Page 488: Interrupt Identification Register (Fiir)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.7 Interrupt Identification Register (FIIR) FIIR consists of bits that identify interrupt sources. For details, see table 16.4. Bit Name Initial Value Description FIFOE1 FIFO Enable 1, 0 FIFOE0 These bits indicate the transmit/receive FIFO setting.
Page 489 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.4 Interrupt Control Function FIIR Setting/Clearing of Interrupt INTID Clearing of INTPEND Priority Type of Interrupt Interrupt Source Interrupt   No interrupt None 1 (high) Receive line status Overrun error, FLSR read parity error, framing error, break...
Page 490: Fifo Control Register (Ffcr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.8 FIFO Control Register (FFCR) FFCR is a write-only register that controls transmit/receive FIFOs. Bit Name Initial Value R/W Description RCVRTRIG1 Receive FIFO Interrupt Trigger Level 1, 0 RCVRTRIG0 These bits set the trigger level of the receive FIFO interrupt.
Page 491: Line Control Register (Flcr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.9 Line Control Register (FLCR) FLCR sets formats of the transmit/receive data. Bit Name Initial Value Description DLAB Divisor Latch Address FDLL and FDLH are placed at the same addresses as the FRBR/FTHR and FIER addresses. This bit selects which register is to be accessed.
Page 492: Modem Control Register (Fmcr)
Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description STOP Stop Bit Specifies the stop bit length for data transmission. For data reception, only the first stop bit is checked regardless of the setting. 0: 1 stop bit 1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data length: 6 to 8 bits) CLS1...
Page 493 Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value Description OUT2 OUT2 • Normal operation Enables or disables the SCIF interrupt. 0: Interrupt disabled 1: Interrupt enabled • Loopback test Internally connected to the DCD input pin. OUT1 OUT1 •...
Page 494: Line Status Register (Flsr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.11 Line Status Register (FLSR) FLSR is a read-only register that indicates the status information of data transmission. Bit Name Initial Value R/W Description RXFIFOERR 0 Receive FIFO Error Indicates that at least one data error (parity error, framing error, or break interrupt) has occurred when the FIFO is enabled.
Page 495 Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description THRE FTHR Empty Indicates that FTHR is ready to accept new data for transmission. • When the FIFO is enabled 0: Transmit data of one or more bytes remains in the transmit FIFO.
Page 496 Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description Framing Error Indicates that the stop bit of the receive data is invalid. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer.
Page 497 Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description Overrun Error Indicates occurrence of an overrun error. • When the FIFO is disabled When reception of the next data has been completed without the receive data in FRBR having been read, an overrun error occurs and the previous data is lost.
Page 498: Modem Status Register (Fmsr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.12 Modem Status Register (FMSR) FMSR is a read-only register that indicates the status of or a change in the modem control pins. Bit Name Initial Value R/W Description Undefined Data Carrier Detect Indicates the inverted state of the DCD input pin.
Page 499: Scratch Pad Register (Fscr)
Section 16 Serial Communication Interface with FIFO (SCIF) Bit Name Initial Value R/W Description DDSR Delta Data Set Ready Indicator Indicates a change in the DSR input signal after the DDSR bit is read. 0: No change in the DSR input signal after FMSR read [Clearing condition] FMSR read...
Page 500: Scif Control Register (Scifcr)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.14 SCIF Control Register (SCIFCR) SCIFCR controls SCIF operations, and is accessible only from the CPU. Bit Name Initial Value R/W Description SCIFOE1 These bits enable or disable PORT output of the SCIF.
Page 501 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.5 SCIF Output Setting Bit 3 in HICR5 0 Bit 7 in SCIFCR Bit 6 in SCIFCR PB7 and PB5 PORT PORT SCIF PORT SCIF PORT SCIF PORT pins P50 pin PORT PORT SCIF...
Page 502: Operation
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4 Operation 16.4.1 Baud Rate The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH, FDLL, and the CKSEL bit in SCIFCR. Table 16.6 shows an example of baud rate settings. Table 16.6 Example of Baud Rate Settings System Clock System Clock...
Page 503: Operation In Asynchronous Communication
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.2 Operation in Asynchronous Communication Figure 16.2 illustrates the typical format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least significant bit), a parity bit, and a stop bit (high level).
Page 504: Initialization Of The Scif
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.3 Initialization of the SCIF Initialization of the SCIF Use an example of the flowchart in figure 16.3 to initialize the SCIF before transmitting or receiving data. Start initialization Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR.
Page 505 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission Figure 16.4 shows an example of the data transmission flowchart. Initialization [1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data.
Page 506 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception Figure 16.5 shows an example of the data reception flowchart. Confirm that the DR flag in FLSR is 1 to ensure that Initialization receive data is in the buffer. When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1, a receive data ready interrupt occurs.
Page 507: Data Transmission/Reception With Flow Control
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.4 Data Transmission/Reception with Flow Control The following shows examples of data transmission/reception for flow control using CTS and RTS. Initialization Figure 16.6 shows an example of the initialization flowchart. Start initialization [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR.
Page 508 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transmission/Reception Standby Figure 16.7 shows an example of the data transmission/reception standby flowchart. [1] When a receive data ready interrupt Initialization occurs, go to the reception flow. [2] When transmit data exists, go to the transmission flow.
Page 509 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transmission Figure 16.8 shows an example of the data transmission flowchart. [1] Confirm that the CTS flag in FMSR is 1. Transmission/reception standby [2] Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is empty.
Page 510 Section 16 Serial Communication Interface with FIFO (SCIF) Suspension of Data Transmission Figure 16.9 shows an example of the data transmission suspension flowchart. [1] Read the DCTS flag in FMSR in the modem Modem status change interrupt status change interrupt processing routine. If the DCTS flag is set to 1, the transmission suspension processing starts.
Page 511 Section 16 Serial Communication Interface with FIFO (SCIF) Data Reception Figure 16.10 shows an example of the data reception flowchart. [1] When data is received, a receive data ready Receive data ready interrupt interrupt occurs. Go to the data reception flow by using this interrupt trigger.
Page 512 Section 16 Serial Communication Interface with FIFO (SCIF) Suspension of Data Reception Figure 16.11 shows an example of the data reception suspension flowchart. [1] When data is received at a trigger level higher than Receive FIFO trigger level interrupt the receive FIFO trigger level specified in the initialization flow, a receive FIFO trigger level interrupt occurs.
Page 513: Data Transmission/Reception Through The Lpc Interface
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.5 Data Transmission/Reception Through the LPC Interface As shown in table 16.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception shown in figures 16.3 to 16.5 to be made from the LPC interface.
Page 514 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.8 shows the range of initialization of the registers related to data transmission/reception through the LPC interface, making a classification by each mode. Table 16.8 Register States System Register Reset SCIFRST REGRST Reset Shutdown Abort...
Page 515 Section 16 Serial Communication Interface with FIFO (SCIF) System Register Reset SCIFRST REGRST Reset Shutdown Abort FMCR LOOP BACK, Initialized Stopped Initialized Initialized Stopped Stopped OUT2, OUT1, RTS, DTR FLSR RXFIFOERR, Initialized Stopped Initialized Initialized Stopped Stopped TEMT, THRE, BI, FE, PE, OE, DR FMSR DDCD, TERI,...
Page 516: Interrupt Sources
Section 16 Serial Communication Interface with FIFO (SCIF) 16.5 Interrupt Sources Table 16.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt source. When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU. The SERIRQ signal of the LPC interface transmits an interrupt request to the host.
Page 517: Section 17 I C Bus Interface (Iic)
Section 17 I C Bus Interface (IIC) Section 17 I C Bus Interface (IIC) This LSI has a two-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 518 Section 17 I C Bus Interface (IIC) • Direct bus drive (SCL/SDA pin)  Ten pins—P52/SCL0, P97/SDA0, PG0/SDAA, PG 1/SCLA, PG2/SDAB, PG3/SCLB, PG4/SDAC, PG5/SCLC, PG6/SDAD, and PG7/SCLD —(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Note: When using this IIC module, make sure to set bits HNDS, FNC1, and FNC0 in ICXR to 1 in the initial settings.
Page 519 Section 17 I C Bus Interface (IIC) (Master) This LSI (Slave 1) (Slave 2) Figure 17.2 I C Bus Interface Connections (Example: This LSI as Master) Rev. 1.00 May 09, 2008 Page 493 of 954 REJ09B0462-0100...
Page 520: Input/Output Pins
Section 17 I C Bus Interface (IIC) 17.2 Input/Output Pins Table 17.1 summarizes the input/output pins used by the I C bus interface. One of four pins can be specified as SCL and SDA input/output pin for IIC_2. Two or more input/output pins should not be specified for one channel.
Page 521: Register Descriptions
Section 17 I C Bus Interface (IIC) 17.3 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR.
Page 522: C Bus Data Register (Icdr)
Section 17 I C Bus Interface (IIC) 17.3.1 C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT).
Page 523: Slave Address Register (Sar)
Section 17 I C Bus Interface (IIC) 17.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 524: Second Slave Address Register (Sarx)
Section 17 I C Bus Interface (IIC) 17.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
Page 525 Section 17 I C Bus Interface (IIC) Table 17.3 Communication Format SARX Operating Mode C bus format • SAR and SARX slave addresses recognized • General call address recognized C bus format • SAR slave address recognized • SARX slave address ignored •...
Page 526: C Bus Mode Register (Icmr)
Section 17 I C Bus Interface (IIC) 17.3.4 C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Initial Bit Name Value Description MSB-First/LSB-First Select 0: MSB-first...
Page 527 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
Page 528 Section 17 I C Bus Interface (IIC) Table 17.4 I C Transfer Rate STCR ICMR Bits 5, and 7 Bit 5 Bit 4 Bit 3 Transfer Rate φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz φ...
Page 529: C Bus Control Register (Iccr)
Section 17 I C Bus Interface (IIC) 17.3.5 C Bus Control Register (ICCR) ICCR controls the I C bus interface and performs interrupt flag confirmation. Initial Bit Name Value Description C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized.
Page 530 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2.
Page 531 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description BBSY R/W* Bus Busy Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: •...
Page 532 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description IRIC R/(W)* I C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
Page 533 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description IRIC R/(W)* Note: When the slave address does not match and the general call address is not detected (with all flags of AAS, AASX, and ADZ cleared to 0), transmission and reception do not proceed.
Page 534 Section 17 I C Bus Interface (IIC) When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer.
Page 535 Section 17 I C Bus Interface (IIC) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State 1↑ — 1↑ — Reception end with ICDRF=0 — — 0↓ — ICDR read with the above state — — — Reception end with ICDRF=1 —...
Page 536 Section 17 I C Bus Interface (IIC) Table 17.6 Flags and Transfer States (Slave Mode) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State — Idle state (flag clearing required) 1↑ 0↓ — 1↑ Start condition detected 1↑/0 — 1↑...
Page 537 Section 17 I C Bus Interface (IIC) BBSY ESTP STOP IRTR AASX AL ACKB ICDRF ICDRE State — — — — — — — Reception end with ICDRF=1 — — 0↓ 0↓ 0↓ — 0↓ — ICDR read with the above state 1↑/0 —...
Page 538: C Bus Status Register (Icsr)
Section 17 I C Bus Interface (IIC) 17.3.6 C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 17.5 and 17.6. Initial Bit Name Value Description ESTP R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode.
Page 539 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description AASX R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Page 540 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 541 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description Acknowledge Bit ACKB Stores acknowledge data. The bit function varies depending on transmit mode and receive mode. Transmit mode: Holds the acknowledge data returned by the receiving device. [Setting condition] •...
Page 542: C Bus Control Initialization Register (Icres)
Section 17 I C Bus Interface (IIC) 17.3.7 C Bus Control Initialization Register (ICRES) ICRES controls IIC internal latch clearance. Initial Bit Name Value Description 7 to 5 — All 0 Reserved The initial value should not be changed. — Reserved IIC Clear 3 to 0 CLR3...
Page 543: C Bus Extended Control Register (Icxr)
Section 17 I C Bus Interface (IIC) 17.3.8 C Bus Extended Control Register (ICXR) ICXR enables or disables the I C bus interface interrupt generation and handshake control, and indicates the status of receive/transmit operations. Initial Bit Name Value Description STOPIM Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the...
Page 544 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description ICDRF Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out.
Page 545 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description ICDRE Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has...
Page 546 Section 17 I C Bus Interface (IIC) Initial Bit Name Value Description ALIE Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. ALSL Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
Page 547: Operation
Section 17 I C Bus Interface (IIC) 17.4 Operation The I C bus interface has an I C bus format and a serial format. 17.4.1 C Bus Data Format The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 17.3. The first frame following a start condition always consists of 9 bits.
Page 548 Section 17 I C Bus Interface (IIC) 1–7 1–7 1–7 DATA DATA Figure 17.5 I C Bus Timing Table 17.7 I C Bus Data Format Symbols Legend Start condition. The master device drives SDA from high to low while SCL is high Slave address.
Page 549: Initialization
Section 17 I C Bus Interface (IIC) 17.4.2 Initialization Initialize the IIC by the procedure shown in figure 17.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) Cancel module stop mode MSTPB4 = 0 (IIC_2) (MSTPCRL, MSTPCRB) Enable the CPU accessing to the IIC control register and data register Set IICE = 1 in STCR...
Page 550 Section 17 I C Bus Interface (IIC) Start Initialize IIC [1] Initialization Read BBSY flag in ICCR [2] Test the status of the SCL and SDA lines. BBSY = 0? Set MST = 1 and [3] Select master transmit mode. TRS = 1 in ICCR Set BBSY =1 and [4] Start condition issuance...
Page 551 Section 17 I C Bus Interface (IIC) The master mode transmission procedure and operations are described below. 1. Initialize the IIC as described in section 17.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3.
Page 552 Section 17 I C Bus Interface (IIC) 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Page 553 Section 17 I C Bus Interface (IIC) Stop condition issuance (master output) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (master output) Data 1 Data 2 [10] (slave output) ICDRE IRIC IRTR ICDR...
Page 554: Master Receive Operation
Section 17 I C Bus Interface (IIC) 17.4.4 Master Receive Operation In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation.
Page 555 Section 17 I C Bus Interface (IIC) The master mode reception procedure and operations are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0 to determine the end of reception.
Page 556 Section 17 I C Bus Interface (IIC) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 557: Slave Receive Operation
Section 17 I C Bus Interface (IIC) 17.4.5 Slave Receive Operation In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address.
Page 558 Section 17 I C Bus Interface (IIC) Slave receive mode [1] Initialization. Select slave receive mode. Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Clear IRIC flag in ICCR ICDRF = 1? [2] Read the receive data remaining unread.
Page 559 Section 17 I C Bus Interface (IIC) The slave mode reception procedure and operations are described below. 1. Initialize the IIC as described in section 17.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
Page 560 Section 17 I C Bus Interface (IIC) Start condition generation [7] SCL is fixed low until ICDR is read (Pin waveform) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address...
Page 561: Slave Transmit Operation
Section 17 I C Bus Interface (IIC) 17.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode.
Page 562 Section 17 I C Bus Interface (IIC) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1.
Page 563 Section 17 I C Bus Interface (IIC) 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1.
Page 564: Iric Setting Timing And Scl Control
Section 17 I C Bus Interface (IIC) 17.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock.
Page 565 Section 17 I C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC Clear IRIC Clear IRIC User processing (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. IRIC User processing Write to ICDR (transmit)
Page 566: Noise Canceler
Section 17 I C Bus Interface (IIC) 17.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 17.21 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 567 Section 17 I C Bus Interface (IIC) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) • Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR •...
Page 568: Interrupt Sources
Section 17 I C Bus Interface (IIC) 17.5 Interrupt Sources The IIC has interrupt source IICI. Table 17.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently.
Page 569: Usage Notes
Section 17 I C Bus Interface (IIC) 17.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly.
Page 570 Section 17 I C Bus Interface (IIC) 4. The I C bus interface specification for the SCL rise time t is 1000 ns or less (300 ns for high- speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication.
Page 571 Section 17 I C Bus Interface (IIC) Table 17.11 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Specifi- φ = φ = φ = φ = φ = Influence cation (Max.) 8 MHz 10 MHz...
Page 572: Module Stop Mode Setting
Section 17 I C Bus Interface (IIC) The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer rate;...
Page 573: Section 18 Smbus 2.0 Interface (Smbus)
Section 18 SMBus 2.0 Interface (SMBUS) Section 18 SMBus 2.0 Interface (SMBUS) This LSI has a one-channel SMBus 2.0 interface (SMBUS). The SMBUS requires channel 0 of the C bus interface (IIC) as the communication module. The SMBUS includes a hardware module that performs the packet error checking (PEC) calculation.
Page 574: Input/Output Pins
Section 18 SMBus 2.0 Interface (SMBUS) 18.2 Input/Output Pins Table 18.1 lists the pins used by the SMBUS. Table 18.1 Pin Configuration Channel Symbol* Input/Output Function SCL0 Input/Output Serial clock input/output pin of SMBUS SDA0 Input/Output Serial data input/output pin of SMBUS Note: The suffix 0 indicating the channel is omitted from later descriptions, i.e.
Page 575: Pec Calculation Data Re-Entry Register (Pecy)
Section 18 SMBus 2.0 Interface (SMBUS) 18.3.2 PEC Calculation Data Re-entry Register (PECY) PECY is a register in which the previous PECZ content is reentered as the PEC calculation is performed on multiple bytes of data. When data is written to PECX, the PECZ content is transferred to PECY at the same time. Initial Bit Name Value...
Page 576: Operation
Section 18 SMBus 2.0 Interface (SMBUS) 18.4 Operation Transfer over the SMBUS is in the same format as transfer over the I C bus interface. The PEC is transferred after the last byte of data, enabling the detection of errors in received data. 18.4.1 SMBus 2.0 Data Format Figure 18.2 is a schematic diagram of the SMBus 2.0 format.
Page 577: Usage Of Pec Calculation Module
Section 18 SMBus 2.0 Interface (SMBUS) Table 18.3 SMBus 2.0 Data Format Symbols Legend Start condition The master device drives SDA from high to low while SCL is high. Slave address The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0.
Page 578: Usage Notes
Section 18 SMBus 2.0 Interface (SMBUS) Start [1] Write H'0000 to PECX and PECY. Initial setting [2] Write transmit/receive data on which PEC calculation Write transmit/receive is required to PECX (byte units). data to PECX Last data? [3] Read PECZ after the PEC calculation of the last transmit/receive data.
Page 579: Section 19 Keyboard Buffer Control Unit (Ps2)
Section 19 Keyboard Buffer Control Unit (PS2) Section 19 Keyboard Buffer Control Unit (PS2) This LSI has two on-chip keyboard buffer control unit (PS2) channels. The PS2 is provided with functions conforming to the PS/2 interface specifications. Data transfer using the PS2 employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc.
Page 580 Section 19 Keyboard Buffer Control Unit (PS2) Internal data bus KBBR KBTR Transmission start KBCR1 (PS2AD, PS2BD) KCLKI KBCRH Control logic Parity KCLK Transmit counter (PS2AC, value KBCR2 PS2BC) KBCRL KCLKO Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend] PS2 data I/O pin KBTR:...
Page 581: Input/Output Pins
Section 19 Keyboard Buffer Control Unit (PS2) Figure 19.2 shows how the PS2 is connected. System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer control unit Interface (This LSI) Figure 19.2 PS2 Connection...
Page 582: Register Descriptions
Section 19 Keyboard Buffer Control Unit (PS2) 19.3 Register Descriptions The PS2 has the following registers for each channel. Table 19.2 Register Configuration Initial Data Bus Channel Register Name Abbreviation Value Address Width Channel 0 Keyboard control register 1_0 KBCR1_0 H'00 H'FEC0 8 Keyboard control register 2_0...
Page 583: Keyboard Control Register 1 (Kbcr1)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.1 Keyboard Control Register 1 (KBCR1) KBCR1 controls data transmission and interrupt, selects parity, and detects transmit error. Initial Bit Name Value Description KBTS Transmit Start Selects start of data transmission or disables transmission.
Page 584 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description KCIF R/(W)* First KCLK Falling Interrupt Flag Indicates that the first falling edge of KCLK is detected. When KCIE and KCIF are set to 1, requests the CPU an interrupt. 0: [Clearing condition] After reading KCIF = 1, 0 is written 1: [Setting condition]...
Page 585: Keyboard Buffer Control Register 2 (Kbcr2)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.2 Keyboard Buffer Control Register 2 (KBCR2) KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first).
Page 586: Keyboard Control Register H (Kbcrh)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.3 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer control unit. Initial Bit Name Value Description KBIOE Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used.
Page 587 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR. When both KBIE and KBF are set to1, an interrupt request is sent to the CPU.
Page 588: Keyboard Control Register L (Kbcrl)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.4 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output. Initial Bit Name Value Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled KCLKO...
Page 589 Section 19 Keyboard Buffer Control Unit (PS2) Initial Bit Name Value Description RXCR3 Receive Counter RXCR2 These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be RXCR1 modified. RXCR0 The receive counter is initialized by a reset and when 0 is written in KBE.
Page 590: Keyboard Data Buffer Register (Kbbr)
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.5 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. The value is valid only when KBF = 1. Initial Bit Name Value Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset or when KBIOE is cleared to 0.
Page 591: Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4 Operation 19.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 592 Section 19 Keyboard Buffer Control Unit (PS2) Flag cleared Receive processing/ error handling KCLK (pin state) Start Parity bit Stop bit (pin state) KCLK (input) KCLK Automatic I/O inhibit (output) KB7 to KB0 Previous data Receive data [1] [2] [3] [4] [5] Figure 19.4 Receive Timing Rev.
Page 593: Transmit Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order.
Page 594: Receive Abort
Section 19 Keyboard Buffer Control Unit (PS2) I/O inhibit KCLK (pin state) Receive Start bit completed Parity Stop bit notification (pin state) KCLK (input) I/O inhibit KCLK (output) KBTE KTER KBTS [9] [10] [11] [6] [7] [8] [1] to [3] Figure 19.6 Transmit Timing 19.4.3 Receive Abort...
Page 595 Section 19 Keyboard Buffer Control Unit (PS2) [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less Receive state than B'1001, write 0 in KCLKO to abort reception.
Page 596 Section 19 Keyboard Buffer Control Unit (PS2) Processing 1 [1] On the system side, drive the KCLK pin low, setting Receive operation ends the I/O inhibit state. normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted.
Page 597: Kclki And Kdi Read Timing
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.4 KCLKI and KDI Read Timing Figure 19.9 shows the KCLKI and KDI read timing. φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI register Internal data bus (read data) Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.9 KCLKI and KDI Read Timing 19.4.5 KCLKO and KDO Write Timing...
Page 598: Kbf Setting Timing And Kclk Control
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.6 KBF Setting Timing and KCLK Control Figure 19.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK 11th fall (pin) Internal KCLK Falling edge signal RXCR3 to B'1010 B'0000 RXCR0 KCLK Automatic I/O inhibit...
Page 599: Receive Timing
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.7 Receive Timing Figure 19.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to N + 1 N + 2 RXCR0 Internal KD (KDI) KBBR7 to KBBR0 Note: * φ...
Page 600: Kclk Fall Interrupt Operation
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.9 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 19.14 shows the setting method and an example of operation.
Page 601: 19.4.10 First Kclk Falling Interrupt
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby mode and watch mode can be cancelled by a first KCLK falling interrupt.
Page 602 Section 19 Keyboard Buffer Control Unit (PS2) • Canceling software standby mode and watch mode Software standby mode and watch mode are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode or watch mode has been shifted (figure 19.17).
Page 603 Section 19 Keyboard Buffer Control Unit (PS2) Software standby mode and watch mode Interrupt control block Falling edge detection circuit Interrupt KCLK Interrupt request vector to CPU generation circuit Interrupt control Figure 19.16 First KCLK Interrupt Path (a) Interrupt timing in software standby mode and watch mode KCLK Software standby mode and watch mode...
Page 604 Section 19 Keyboard Buffer Control Unit (PS2) KCLK First KCLK falling edge Automatic clear Internal flag Interrupt generated Interrupt accepted (Accepted at any timing) Figure 19.18 Internal Flag of First KCLK Falling Interrupt in Software Standby Mode and Watch Mode Rev.
Page 605: Usage Notes
Section 19 Keyboard Buffer Control Unit (PS2) 19.5 Usage Notes 19.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected.
Page 606: Kd Output By Kdo Bit (Kbcrl) And By Automatic Transmission
Section 19 Keyboard Buffer Control Unit (PS2) 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission Figure 19.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0.
Page 607: Section 20 Lpc Interface (Lpc)
Section 20 LPC Interface (LPC) Section 20 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock.
Page 608 Section 20 LPC Interface (LPC) • Power-down modes and interrupts  The LPC module can be shut down by inputting the LPCPD signal.  Three pins, PME, LSMI, and LSCI, are provided for general input/output. Rev. 1.00 May 09, 2008 Page 582 of 954 REJ09B0462-0100...
Page 609 Section 20 LPC Interface (LPC) Figure 20.1 shows a block diagram of the LPC. Module data bus Parallel → serial conversion TWR0MW IDR4 SERIRQ IDR3 TWR1 to TWR15 IDR2 IDR1 SIRQCR0 to 4 CLKRUN HISEL Cycle detection LPCPD Control logic Serial →...
Page 610: Input/Output Pins
Section 20 LPC Interface (LPC) 20.2 Input/Output Pins Table 20.1 lists the LPC pin configuration. Table 20.1 Pin Configuration Name Abbreviation Port Function LPC address/ LAD3 to LAD0 P33 to P30 I/O Cycle type/address/data signals data 3 to 0 serially (4-signal-line) transferred in synchronization with LCLK LFRAME LPC frame...
Page 611: Register Descriptions
Section 20 LPC Interface (LPC) 20.3 Register Descriptions The LPC has the following registers. Table 20.2 Register Configuration Initial Data Bus Register Name Abbreviation Slave Host Value Address Width  Host interface control register 0 HICR0 H'00 H'FE40  Host interface control register 1 HICR1 H'00 H'FE41...
Page 612 Section 20 LPC Interface (LPC) Initial Data Bus Register Name Abbreviation Slave Host Value Address Width Bidirectional data register 0MW TWR0MW H'00 H'FE20 Bidirectional data register 0SW TWR0SW H'00 H'FE20 Bidirectional data register 1 TWR1 H'00 H'FE21 Bidirectional data register 2 TWR2 H'00 H'FE22...
Page 613: Host Interface Control Registers 0 And 1 (Hicr0 And Hicr1)
Section 20 LPC Interface (LPC) 20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface.
Page 614 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  FGA20E Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output.
Page 615 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  PMEE PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. PMEE PMEB : PME output disabled, other function...
Page 616 Section 20 LPC Interface (LPC) • HICR1 Initial Value Bit Name Slave Host Description  LPCBSY LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state • Bus idle, or transfer cycle not subject to processing is in progress •...
Page 617 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  CLKREQ LCLK Request Indicates that the LPC interface's SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] • LPC hardware reset or LPC software reset •...
Page 618 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  LRSTB LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 20.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] •...
Page 619: Host Interface Control Registers 2 And 3 (Hicr2 And Hicr3)
Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  LSCIB LSCI output Bit Controls LSCI output in combination with the LSCIE bit IN HICR0. For details, refer to description on the LSCIE bit in HICR0. 20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3) HICR2 controls interrupts to an LPC interface slave (this LSI).
Page 620 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description R/(W)*  ABRT LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] •...
Page 621 Section 20 LPC Interface (LPC) Initial Bit Name Value Slave Host Description  IBFIE1 IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled ...
Page 622: Host Interface Control Register 4 (Hicr4)
Section 20 LPC Interface (LPC) 20.3.3 Host Interface Control Register 4 (HICR4) HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface slave (this LSI). Initial Bit Name Value Slave Host Description   Reserved The initial value should not be changed.
Page 623: Host Interface Control Register 5 (Hicr5)
Section 20 LPC Interface (LPC) 20.3.4 Host Interface Control Register 5 (HICR5) HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts. Initial Bit Name Value Slave Host Description  OBEIE Output Buffer Empty Interrupt Enable Enables or disables OBEI interrupts (for this LSI).
Page 624: Lpc Channel 1 Address Registers H And L (Ladr1H And Ladr1L)
Section 20 LPC Interface (LPC) 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L) LADR1 sets the LPC channel 1 host address. The LADR1 contents must not be changed while channel 1 is operating (while LPC1E is set to 1). •...
Page 625: Lpc Channel 2 Address Registers H And L (Ladr2H And Ladr2L)
Section 20 LPC Interface (LPC) • Host select register I/O Address Transfer Cycle Bits 5 to 3 Bit 2 Bits 1 and 0 Host Select Register Bits 15 to 3 in LADR1 Bits 1 and 0 in LADR1 I/O write IDR1 write (data) Bits 15 to 3 in LADR1 Bits 1 and 0 in LADR1...
Page 626 Section 20 LPC Interface (LPC) • LADR2L Initial Value Bit Name Slave Host Description  Bit 7 Channel 2 Address Bits 7 to 3  Bit 6 Set the LPC channel 2 host address.  Bit 5  Bit 4 ...
Page 627: Lpc Channel 3 Address Registers H And L (Ladr3H And Ladr3L)
Section 20 LPC Interface (LPC) 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L) LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Page 628 Section 20 LPC Interface (LPC) When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored.
Page 629: Lpc Channel 4 Address Registers H And L (Ladr4H And Ladr4L)
Section 20 LPC Interface (LPC) 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L) LADR4 sets the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). •...
Page 630: Input Data Registers 1 To 4 (Idr1 To Idr4)
Section 20 LPC Interface (LPC) • Host select register I/O Address Transfer Bits 5 to 3 Bit 2 Bits 1 and 0 Cycle Host Select Register Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4 I/O write IDR4 write (data) Bits 15 to 3 in LADR4 Bits 1 and 0 in LADR4...
Page 631: Bidirectional Data Registers 0 To 15 (Twr0 To Twr15)
Section 20 LPC Interface (LPC) 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave (this LSI) and host. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host and the slave addresses.
Page 632 Section 20 LPC Interface (LPC) • STR1 Bit Name Initial Value Slave Host Description DBU17 Defined by User DBU16 The user can use these bits as necessary. DBU15 DBU14 C/D1 Command/Data When the host writes to IDR1, bit 2 of the I/O address is written into this bit to indicate whether IDR1 contains data or a command.
Page 633 Section 20 LPC Interface (LPC) • STR2 Bit Name Initial Value Slave Host Description DBU27 Defined by User DBU26 The user can use these bits as necessary. DBU25 DBU24 C/D2 Command/Data When the host writes to IDR2, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command.
Page 634 Section 20 LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) Bit Name Initial Value Slave Host Description IBF3B Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition]...
Page 635 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description C/D3 Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data.
Page 636 Section 20 LPC Interface (LPC) • STR3 (TWRE = 0 and SELSTR3 = 1) Bit Name Initial Value Slave Host Description DBU37 Defined by User DBU36 The user can use these bits as necessary. DBU35 DBU34 C/D3 Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command.
Page 637 Section 20 LPC Interface (LPC) • STR4 Bit Name Initial Value Slave Host Description DBU47 Defined by User DBU46 The user can use these bits as necessary. DBU45 DBU44 C/D4 Command/Data Flag When the host writes to IDR4, bit 2 of the I/O address is written into this bit to indicate whether IDR4 contains data or a command.
Page 638: Serirq Control Register 0 (Sirqcr0)
Section 20 LPC Interface (LPC) 20.3.13 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Bit Name Initial Value Slave Host Description  Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
Page 639 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE3B Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled.
Page 640 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE2 Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled.
Page 641 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ1E1 Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled.
Page 642: Serirq Control Register 1 (Sirqcr1)
Section 20 LPC Interface (LPC) 20.3.14 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. Bit Name Initial Value Slave Host Description  Host IRQ11 Interrupt Enable 3 IRQ11E3 0 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write.
Page 643 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E3 Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled.
Page 644 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ11E2 0 Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled.
Page 645 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E2 Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled.
Page 646: Serirq Control Register 2 (Sirqcr2)
Section 20 LPC Interface (LPC) 20.3.15 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. Bit Name Initial Value Slave Host Description  IEDIR3 Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable...
Page 647 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ11E4 0 Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ11 interrupt request by OBF4 and IRQE11E4 is disabled.
Page 648 Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  IRQ9E4 Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ9 interrupt request by OBF4 and IRQE9E4 is disabled.
Page 649: Serirq Control Register 3 (Sirqcr3)
Section 20 LPC Interface (LPC) Bit Name Initial Value Slave Host Description  SMIE4 Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write. 0: Host SMI interrupt request by OBF4 and SMIE4 is disabled.
Page 650: Serirq Control Register 4 (Sirqcr4)
Section 20 LPC Interface (LPC) 20.3.17 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 is used to select the SERIRQ interrupt requests of the SCIF. Initial Bit Name Value Slave Host Description 7 to 4   All 0 Reserved The initial value should not be changed. ...
Page 651: Scif Address Register (Scifadrh, Scifadrl)
Section 20 LPC Interface (LPC) 20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) SCIFADR sets the host addresses of the SCIF. Do not change the contents of SCIFADR during operation of the SCIF (i.e. while SCIFE is set to 1). • SCIFADRH Initial Bit Name Value...
Page 652: Host Interface Select Register (Hisel)
Section 20 LPC Interface (LPC) 20.3.19 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Initial Bit Name Value Slave Host Description ...
Page 653: Operation
Section 20 LPC Interface (LPC) 20.4 Operation 20.4.1 LPC interface Activation The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0 and LPC4E in HICR4. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins.
Page 654 Section 20 LPC Interface (LPC) In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B'0000 in the slave's synchronization return cycle, but with the LPC of this LSI a value of B'0000 always returns.
Page 655 Section 20 LPC Interface (LPC) LCLK LFRAME LAD3 to Start ADDR Sync Data Start LAD0 Cycle type, direction, and size Number of clocks Figure 20.2 Typical LFRAME Timing LCLK LFRAME Start ADDR Sync LAD3 to LAD0 Master will drive high Cycle type, Slave must stop driving direction,...
Page 656: Gate A20
Section 20 LPC Interface (LPC) 20.4.3 Gate A20 The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0.
Page 657 Section 20 LPC Interface (LPC) Start Host write H'D1 command received? Wait for next byte Host write Data byte? Write bit 1 of data byte to the bit of GA20 in DR Figure 20.4 GA20 Output Rev. 1.00 May 09, 2008 Page 631 of 954 REJ09B0462-0100...
Page 658 Section 20 LPC Interface (LPC) Table 20.5 Fast Gate A20 Output Signals Internal CPU Interrupt Flag GA20 C/D1 Data/Command (IBF) (P81) Remarks H'D1 command Turn-on sequence 1 data* H'FF command Q (1) H'D1 command Turn-off sequence 0 data* H'FF command Q (0) H'D1 command Turn-on sequence...
Page 659: Lpc Interface Shutdown Function (Lpcpd)
Section 20 LPC Interface (LPC) 20.4.4 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown.
Page 660 Section 20 LPC Interface (LPC) Table 20.6 shows the scope of the LPC interface pin shutdown. Table 20.6 Scope of LPC Interface Pin Shutdown Scope of Abbreviation Port Shutdown Notes LAD3 to LAD0 P33 to P30 Hi-Z LFRAME Input Hi-Z LRESET Input LPC hardware reset function is active...
Page 661 Section 20 LPC Interface (LPC) Table 20.7 Scope of Initialization in Each LPC interface Mode System Items Initialized Reset LPC Reset Shutdown LPC transfer cycle sequencer (internal state), LPCBSY and ABRT Initialized Initialized Initialized flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and Initialized Initialized Initialized...
Page 662 Section 20 LPC Interface (LPC) Figure 20.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3 to LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 20.5 Power-Down State Termination Timing Rev.
Page 663: Lpc Interface Serialized Interrupt Operation (Serirq)
Section 20 LPC Interface (LPC) 20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt.
Page 664 Section 20 LPC Interface (LPC) Table 20.8 Serialized Interrupt Transfer Cycle Frame Configuration Serial Interrupt Transfer Cycle Frame Drive Number Count Contents Source of States Notes Start Slave In quiet mode only, slave drive possible in first Host state, then next 3 states 0-driven by host IRQ0 Slave IRQ1...
Page 665: Lpc Interface Clock Start Request
Section 20 LPC Interface (LPC) In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state.
Page 666: Interrupt Sources
Section 20 LPC Interface (LPC) 20.5 Interrupt Sources 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively.
Page 667: Smi, Hirq1, Hirq3, Hirq4, Hirq5, Hirq6, Hirq7, Hirq8, Hirq9
Section 20 LPC Interface (LPC) 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF.
Page 668 Section 20 LPC Interface (LPC) Table 20.10 HIRQ Setting and Clearing Conditions when LPC Channels are Used Host Interrupt Setting Condition Clearing Condition HIRQ1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, from bit IRQ1E1 and writes 1 or host reads ODR1 HIRQ12 Internal CPU writes to ODR1, then reads 0...
Page 669 Section 20 LPC Interface (LPC) Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used Host Interrupt Setting Condition Clearing Condition HIRQi Internal CPU sets the corresponding Reads FMSR and clears the DDCD (i = 1 to 15) SERIRQ host interrupt request for the bit in FMSR SCIF in SIRQCR4 (for details, see the...
Page 670: Usage Note
Section 20 LPC Interface (LPC) 20.6 Usage Note 20.6.1 Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted.
Page 671 Section 20 LPC Interface (LPC) Table 20.12 Host Address Example Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 IDR3 H'A24A and H'A24E H'3FD0 and H'3FD4 ODR3 H'A24A H'3FD0 STR3 H'A24E H'3FD4 TWR0MW H'A250 H'3FC0 TWR0SW H'A250 H'3FC0 TWR1...
Page 672 Section 20 LPC Interface (LPC) Rev. 1.00 May 09, 2008 Page 646 of 954 REJ09B0462-0100...
Page 673: Section 21 Fsi Interface
Section 21 FSI Interface Section 21 FSI Interface This LSI incorporates the SPI flash memory serial interface (FSI) that supports the communication between this LSI and SPI flash memory. The FSI performs communications using the LPC or CPU of this LSI as a master. 21.1 Features Figure 21.1 shows a block diagram of the FSI.
Page 674 Section 21 FSI Interface FSICMDI, FSIWI FSITEI, FSIRXI FSICR1/2 FSIINS FSIBNR SLCR FSIRDINS FSISTR FSIPPINS FSIHBARH/L FSISR LCLK Address-Change FSISS LAD 3 to 0 Trans/Rev LFRAME FSICK CMDHBRH/L Controller FSILSTR1/2 FSIGPR1 to F FSIARLH/M/L FSIWDHH/HL/LH/LL FSITDR FSIRDR FSICMDR FSIDO FSISFR FSIDI [Legend] FSISFR: FSI shift register...
Page 675: Input/Output Pins
Section 21 FSI Interface 21.2 Input/Output Pins Table 21.1 shows the input/output pins of the FSI. Table 21.1 Pin Configuration Pin Name Symbol Function FSI slave select FSISS Output FSI slave select signal FSI clock FSICK Output FSI clock signal FSI master data input FSIDI Input...
Page 676: Register Description
Section 21 FSI Interface 21.3 Register Description The FSI consists of the following registers. Table 21.3 List of Register Addresses Initial Register Name Abbreviation Host Value Address  FSI control register 1 FSICR1 H'00 H'FC90  FSI control register 2 FSICR2 H'00 H'FC91...
Page 677 Section 21 FSI Interface Initial Register Name Abbreviation Host Value Address FSI general-purpose register 1 FSIGPR1 H'00 H'FC57 FSI general-purpose register 2 FSIGPR2 H'00 H'FC58 FSI general-purpose register 3 FSIGPR3 H'00 H'FC59 FSI general-purpose register 4 FSIGPR4 H'00 H'FC5A FSI general-purpose register 5 FSIGPR5 H'00 H'FC5B...
Page 678: Fsi Control Register 1 (Fsicr1)
Section 21 FSI Interface 21.3.1 FSI Control Register 1 (FSICR1) The FSICR1 control bits are classified into three functionalities: resetting the FSI internal signals, enabling/disabling FSI functions, and selecting FSI functions. Initial Bit Name Value Host Description R/W  SRES Software Reset Controls initialization of the FSI internal sequencer.
Page 679: Fsi Control Register 2 (Fsicr2)
Section 21 FSI Interface Initial Bit Name Value EC Host Description  CPHS CPHS: Selects the polarity of the FSICK clock.  CPOS CPOS: Selects the phase of the FSICK clock. CPHS CPOS Initial value of FSICK: Low level Data changes at the FSICK falling edge.
Page 680 Section 21 FSI Interface Initial Bit Name Value Host Description  FSI Reception Enable Controls FSI reception and indicates reception status in combination with the LFBUSY bit. 0: FSI reception wait state [Clearing condition] When FSI data reception is completed. 1: When LFBUSY = 0: Starts reception.
Page 681: Fsi Byte Count Register (Fsibnr)
Section 21 FSI Interface 21.3.3 FSI Byte Count Register (FSIBNR) The FSIBNR sets the number of bytes to be transmitted or received by the FSI. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. Initial Bit Name Value...
Page 682: Fsi Instruction Register (Fsiins)
Section 21 FSI Interface Initial Bit Name Value Host Description  2 to 0 RBN2 Receive Byte Count 2-0 RBN1 These bits specify the number of data bytes to be received. After the FSI reception operation ends RBN0 (when FSIRXI in FSISTR is 1), the RBN value is decremented (−1) each time FSIRDR is read.
Page 683: Fsi Instruction Register (Fsirdins)
Section 21 FSI Interface 21.3.5 FSI Instruction Register (FSIRDINS) FSIRDINS sets a read operation instruction to be sent to FSITDR during read operation. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be modified during initialization.
Page 684 Section 21 FSI Interface Initial Bit Name Value Host Description  Transmit Data Register Full Indicates whether or not there is data to be written by the EC (this LSI). 0: There is no write data. [Clearing condition] When write data transmission to the SPI flash memory is completed.
Page 685: Fsi Transmit Data Registers 0 To 7 (Fsitdr0 To Fsitdr7)
Section 21 FSI Interface 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7) FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the SPI flash memory.
Page 686: Fsi Access Host Base Address Registers H And L (Fsihbarh And Fsihbarl)
Section 21 FSI Interface 21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL) FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to convert the host address to the SPI flash memory address. The input range of the host address will be determined based on the host start address set in these registers and the memory size set in FSISR.
Page 687: Fsi Flash Memory Size Register (Fsisr)
Section 21 FSI Interface 21.3.11 FSI Flash Memory Size Register (FSISR) FSISR sets the size of SPI flash memory. The host input address range will be determined based on the size set in this register. Note that the host input address should not be greater than the SPI flash memory capacity.
Page 688: Fsi Command Host Base Address Registers H And L (Cmdhbarh And Cmdhbarl)
Section 21 FSI Interface 21.3.12 FSI Command Host Base Address Registers H and L (CMDHBARH and CMDHBARL) CMDHBARH and CMDHBARL set the upper 16 bits of the host start address which is necessary to set a command address. The lower 16 bits of the host start address range from H'F000 to H'F00F.
Page 689: Fsi Lpc Command Status Register 1 (Fsilstr1)
Section 21 FSI Interface 21.3.14 FSI LPC Command Status Register 1 (FSILSTR1) FSILSTR1 indicates the LPC internal status. Initial Bit Name Value Host Description CMDBUSY 0 R/W* R FSI Command Busy Flag 0: The FSI command execution is completed. [Clearing condition] •...
Page 690 Section 21 FSI Interface Initial Bit Name Value Host Description FSIDMYE FSI Dummy Enable 0: Disables FSI dummy. 1: Enables FSI dummy. FSIWBUSY 0 R/W* R FSI Write Busy Flag 0: FSI write transfer is completed. [Clearing condition] • When this bit is read as 1 and then written with 0. 1: FSI write in transferring [Setting condition] •...
Page 691: Fsi Lpc Command Status Register 2 (Fsilstr2)
Section 21 FSI Interface 21.3.15 FSI LPC Command Status Register 2 (FSILSTR2) FSILSTR2 indicates the LPC internal status. Initial Bit Name Value Host Description 7 to 5   All 0 Reserved The initial value should not be modified.  FSIDWBUSY FSI Direct Write Busy Flag Indicates a FSI write transfer status during LPC-...
Page 692: Fsi General-Purpose Registers 1 To F (Fsigpr1 To Fsigprf)
Section 21 FSI Interface 21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) FSIGPR1 to FSIGPRF store data such as the result of FSI command interrupt processing. • FSIGPR1 to FSIGPRF Initial Bit Name Value Host Description 7 to 0 bit 7 to bit 0 All 0 These bits store results of FSI command interrupt processing.
Page 693: Fsi Address Registers H, M, And L (Fsiarh, Fsiarm, And Fsiarl)
Section 21 FSI Interface Initial Bit Name Value Host Description  FLDCT FSI LPC Direct Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: LPC-SPI indirect transfer 1: LPC-SPI direct transfer ...
Page 694: Fsi Write Data Registers Hh, Hl, Lh, And Ll (Fsiwdrhh, Fsiwdrhl, Fsiwdrlh, And Fsiwdrll)
Section 21 FSI Interface • FSIARL Initial Bit Name Value Host Description  7 to 0 bit 7 to bit 0 All 0 These bits store bits [7:0] of the SPI flash memory address. 21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL) FSIWDR stores data to be written to the SPI flash memory.
Page 695 Section 21 FSI Interface • FSIWDRLH Initial Bit Name Value Host Description  7 to 0 bit 15 to All 0 These bits store bits [15:8] of the SPI flash memory bit 8 write data. • FSIWDRLL Initial Bit Name Value Host Description ...
Page 696: Operation
Section 21 FSI Interface 21.4 Operation 21.4.1 LPC/FW Memory Cycles In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0 synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error occurrence;...
Page 697 Section 21 FSI Interface LPC Memory Read Cycles LPC Memory Write Cycles State Counts Content Driven by Value (3 to 0) Content Driven by Value (3 to 0) Slave 0000 Turn-around None ZZZZ Synchronization Data 1 Slave bit 3 to bit 0 Wait* Slave 0110...
Page 698: Spi Flash Memory Transfer
Section 21 FSI Interface FW Memory Read Cycles FW Memory Write Cycles State Counts Content Driven by Value (3 to 0) Content Driven by Value (3 to 0) Turn-around Slave 1111 Turn-around Slave 1111 (recovery) (recovery) Turn-around None ZZZZ Turn-around None ZZZZ Note:...
Page 699: Flash Memory Instructions
Section 21 FSI Interface 21.4.3 Flash Memory Instructions Table 21.6 lists the flash memory instructions (INS). Table 21.6 List of Instructions (INS) Instruction Name Description WREN Sets write-enable WRDI Resets write-enable RDSR Reads status register WRSR Writes status register READ Reads SPI flash memory Fast-Read Fast-reads SPI flash memory...
Page 700: Fsi Memory Cycle (Direct Transfer Between Lpc And Spi)
Section 21 FSI Interface 21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI) The FSI supports direct transfer between the host and SPI flash memory. If the host address input in LPC/FW memory write cycle matches the host address set in FSIHBARH, FSIHBARL, or FSISR, the FSI memory cycle starts.
Page 701 Section 21 FSI Interface Byte/Page-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively.
Page 702 Section 21 FSI Interface LCLK LFRAME LAD[3:0] ST CT SY TAR ADDR DATA WAIT φ FSIAR[23:0] H'06-4A-70 FSIWDR[31:0] H'67-45-23-01 FSIPPINS[7:0] H'02 FSICR2 TE bit FSITDR7 to H'67-45-23-01-70-4A-06-02 FSITDR0 FSISTR OBF bit FSISS FSICK (CPOS = CPHS = 0) H'02->06->4A->70->01->23->45->67 FSIDO Figure 21.5 Page-Program Instruction Execution Timing Rev.
Page 703 Section 21 FSI Interface AAI-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR, respectively.
Page 704 Section 21 FSI Interface LCLK LFRAME LAD[3:0] ADDR DATA TAR WAIT SY TAR φ FSIAR[23:0] H'06-4A-70 FSIWDR[31:0] H'23 FSICR2 TE bit FSITDR7 to H'23-AF FSITDR0 FSISTR OBF bit FSISS FSICK (CPOS = CPHS =0) FSIDO H'AF->23 Figure 21.7 AAI-Program Instruction Execution Timing (Second and Following Bytes) Read Instructions If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI...
Page 705 Section 21 FSI Interface First receive data H'01 FSIRDR3 Internal register Second receive data H'23 H'67_45_23_01 Third receive data H'45 Fourth receive data H'67 FSIRDR0 FSIAR[23:0] FSITDR3 FSIAR[7:0] H'70 H'06_4A_70 FSIAR[15:8] H'4A FSIAR[23:16] H'06 FSIRDINS[7:0] H'03 H'03 FSITDR0 FSISFR FSIDI FSIDO Figure 21.8 Data Transfer to FSIRDR (Example) LCLK...
Page 706 Section 21 FSI Interface Fast-Read Instruction If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is set to 1, the host address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is stored in FSIRDINS in advance are transferred to FSITDR.
Page 707: Fsi Memory Cycle (Lpc-Spi Command Transfer)
Section 21 FSI Interface 21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer) The FSI supports instructions other than Byte/Page-Program instructions, AAI-Program instruction, Read instruction, and Fast-Read instruction by using an LPC-SPI command transfer. FSI Command Space Specific host address space can be used as FSI command space according to the CMDHBAR settings.
Page 708 Section 21 FSI Interface FSI Command Write If an LPC/FW memory write cycle for the FSI command space occurs, the FSI performs the FSI- FLASH command write operation. Figure 21.12 shows an example of FSI Command write operation. CMDHBAR: H'EFFF H'EFFF_0000 FSICMDR[7:0] H'EFFF_F000...
Page 709 Section 21 FSI Interface FSI Command Read Figure 21.13 shows an example of FSI command read. CMDHBAR: H'EFFF ∗ H'EFFF_0000 H'EFFF_F000 FSIST LPC internal flags CMD0 CMD1 FSIGPR1 FSIGPR2 to D EC CPU write FSIGPRE CMDE CMDF FSIGPRF H'EFFF_F00F H'EFFF_FFFF Host address Note: The upper 16 bits of the host address are set to the value in the CMDHBAR register.
Page 710 Section 21 FSI Interface FSI Dummy Write Figure 21.14 shows an example of FSI dummy write. FSI Dummy Write FSIHBAR: H'231F FSIDMYE FSISR: H'00 (1 MB) CMDHBAR: H'EFFF FSIWDR[31:0] H'73 H'2325_4A76 H'0000_0073 Host address FSIAR[23:0] H'06_4A76 Byte-Program FSIDMYE Flash memory FSIWDR[31:0] H'232E_1BC3 H'0F_1BC3...
Page 711 Section 21 FSI Interface FSI Command Usage Example 1 (SPI Flash Memory Erasure) The FSI commands enable the execution of several instructions for the SPI flash memory. Figure 21.15 shows an example of executing the SPI flash memory erasure instruction. FSIHBAR: H'231F FSICMDR[7:0] FSISR: H'00 (1 MB)
Page 712 Section 21 FSI Interface STEP1 STEP2 STEP3 φ Cleared by the CPU FSIDMYE Written by the CPU FSICMDI Cleared by the CPU Cleared by the CPU Cleared by the CPU Cleared by the CPU CMDBUSY LPC_ADDR H'EFFF_F000 H'2325_4A76 H'EFFF_F000 FSIAR[23:0] H'06_4A76 Automatically cleared Written by the CPU...
Page 713 Section 21 FSI Interface 4. Execute the SPI flash memory erasure instruction.  Set the TE bit in FSICR2 to 1.  Set the TBN bit in FSIBNR to 4-byte transfer.  Write the FSI address stored in FSIAR to FSITDR1 to FSITDR3. ...
Page 714 Section 21 FSI Interface Step 1: 1. Write a status read setting command (Host). 2. Generate an FSICMDI interrupt request. 3. Clear the FSICMDI bit in FSILSTR1 to 0. 4. Check that the CMDBUSY bit in FSILSTR1 is set to 1 and that the FSICMDI bit in FSILSTR1 is cleared to 0 (Host).
Page 715: Spi Flash Memory Write Operation Mode
Section 21 FSI Interface 21.4.6 SPI Flash Memory Write Operation Mode The write operation to the SPI flash memory in the LPC/FW memory write cycles can be classified into the following four operation modes, depending or the state of FLDCT and FLWAIT.
Page 716: Reset Conditions
Section 21 FSI Interface 21.5 Reset Conditions The FSI supports the LPC shut-down mode. The range of initialization in each mode is shown in table 21.8. Table 21.8 Range of Initialization of FSI in Each Mode System Register Name Reset LPC Reset Shutdown LPC Abort...
Page 717 Section 21 FSI Interface System Register Name Reset LPC Reset Shutdown LPC Abort FSI Reset FSICR1 Bits 7 to 0 Initialized Retained Retained Retained Retained FSICR2 Bits 7 and 6 Initialized Retained Retained Retained Initialized Bits 5 to 0 Initialized Retained Retained Retained...
Page 718: Interrupt Sources
Section 21 FSI Interface 21.6 Interrupt Sources The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read transfer.
Page 719: Section 22 A/D Converter
Section 22 A/D Converter Section 22 A/D Converter This LSI includes one unit (unit 0) of successive-approximation-type 10-bit A/D converter that allows up to twelve analog input channels to be selected. Figure 22.1 shows a block diagram for unit 0. 22.1 Features •...
Page 720 Section 22 A/D Converter Internal Module data bus data bus 10-bit A/D φ – φ/2 Control circuit φ/4 Comparator φ/8 Sample-and- hold circuit ADI interrupt AN10 signal AN11 Conversion start trigger from TPU or 8-bit timer [Legend] ADCR: A/D control register ADDRD: A/D data register D ADCSR:...
Page 721: Input/Output Pins
Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The AVref pin is a reference voltage pin for the A/D converter. The twelve analog input pins are divided into two channel sets: analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0 and analog input pins 8 to 11 (AN8 to AN11) comprising channel set 1.
Page 722: Register Descriptions
Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. Table 22.2 Register Configuration Data Bus Register Name Abbreviation Initial Value Address Width A/D data register A ADDRA H'0000 H'FC00 A/D data register B ADDRB H'0000 H'FC02 A/D data register C ADDRC...
Page 723: A/D Control/Status Register (Adcsr)
Section 22 A/D Converter Table 22.3 Analog Input Channels and Corresponding ADDR Analog Input Channel A/D Data Register to Store A/D Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1) Conversion Results ADDRA ADDRB AN10 ADDRC AN11 ADDRD ...
Page 724 Section 22 A/D Converter Bit Name Initial Value R/W Description ADST R/W A/D Start When this bit is cleared to 0, A/D conversion stops and enters wait state. When this bit is set to 1 by a conversion start trigger from software, TPU, or TMR, A/D conversion starts.
Page 725: A/D Control Register (Adcr)
Section 22 A/D Converter 22.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Name Initial Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 Enable the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by conversion trigger from 10: A/D conversion start by conversion trigger from...
Page 726 Section 22 A/D Converter Bit Name Initial Value Description  Reserved This bit is always read as 0 and cannot be modified. [Legend] X: Don't care Set the clock so that ADCLK ≤ 10 MHz. Note: Rev. 1.00 May 09, 2008 Page 700 of 954 REJ09B0462-0100...
Page 727: Operation
Section 22 A/D Converter 22.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. First, select the clock used in A/D conversion. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion.
Page 728: Scan Mode
Section 22 A/D Converter 22.4.2 Scan Mode In scan mode, A/D conversion is performed sequentially on the specified channels (max. four channels or eight channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software, the TPU, or the TMR, A/D conversion starts on the first channel in the selected channel set.
Page 729: Input Sampling And A/D Conversion Time
Section 22 A/D Converter 22.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion.
Page 730: Interrupt Source
Section 22 A/D Converter Table 22.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. ...
Page 731: A/D Conversion Accuracy Definitions
Section 22 A/D Converter 22.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 22.3). •...
Page 732 Section 22 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 Quantization error H'002 H'001 H'000 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 22.3 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error...
Page 733: Usage Notes
Section 22 A/D Converter 22.7 Usage Notes 22.7.1 Module Stop Mode Setting The A/D converter operation can be enabled or disabled using the module stop control register. With the initial setting, the A/D converter is stopped. Register access is enabled by canceling module stop mode.
Page 734: Influences On Absolute Accuracy
Section 22 A/D Converter 22.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss.
Page 735: Notes On Noise Countermeasures
Section 22 A/D Converter 22.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage of the analog input pins (AN0 to AN11) and analog reference voltage pin (AVref) due to an abnormal voltage such as an excessive surge should be connected between AVcc and AVss, as shown in figure 22.6.
Page 736: Module Stop Mode Setting
Section 22 A/D Converter 10 k Ω AN0 to AN11 To A/D converter 20 pF Note: Values are reference values. Figure 22.7 Analog Input Pin Equivalent Circuit 22.7.7 Module Stop Mode Setting When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to the current as during A/D conversion.
Page 737 Section 22 A/D Converter Setting the TRGS1 and TRGS0 bits in ADCR according to the procedure overleaf invalidates the external trigger input. See figure 22.8 for details of the procedure in cases where 2. or 3. is applicable. Extaernal trigger shut off? ADCR.
Page 738 Section 22 A/D Converter Rev. 1.00 May 09, 2008 Page 712 of 954 REJ09B0462-0100...
Page 739: Section 23 Ram
Section 23 RAM Section 23 RAM This LSI has 4 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 740 Section 23 RAM Rev. 1.00 May 09, 2008 Page 714 of 954 REJ09B0462-0100...
Page 741: Section 24 Flash Memory
Section 24 Flash Memory Section 24 Flash Memory The flash memory has the following features. Figure 24.1 is a block diagram of the flash memory. 24.1 Features • Size Product Classification ROM Size ROM Address H8S/2112R R4F2112R 96 kbytes H'000000 to H'017FFF •...
Page 742 Section 24 Flash Memory Internal address bus Internal data bus (16 bits) FCCS FPCS Memory MAT unit FECS Control unit User MAT: 96 kbytes FKEY User boot MAT: 8 kbytes FTDAR FMATS Flash memory Operating Mode pins mode [Legend] FCCS: Flash code control/status register FPCS: Flash program code select register...
Page 743: Mode Transition Diagram
Section 24 Flash Memory 24.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 24.2. Although the flash memory can be read in user mode, it cannot be programmed or erased.
Page 744 Section 24 Flash Memory Programmer Item Boot Mode User Program Mode User Boot Mode Mode  Reset initiation MAT Embedded User MAT User boot MAT* program storage area  Transition to user Changing mode Changing FLSHE bit Changing mode mode and reset setting and reset...
Page 745: Flash Memory Mat Configuration
Section 24 Flash Memory 24.3 Flash Memory MAT Configuration This LSI's flash memory is configured by the 96-kbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS.
Page 746: Block Structure
Section 24 Flash Memory 24.4 Block Structure Figure 24.4 shows the 96-kbyte block structure. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames indicates the addresses. The 96-kbyte user MAT is divided into two 32-kbyte blocks and eight 4-kbyte blocks. The user MAT can be erased in these block units.
Page 747: Programming/Erasing Interface
Section 24 Flash Memory 24.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters.
Page 748 Section 24 Flash Memory Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM).
Page 749: Input/Output Pins
Section 24 Flash Memory 24.6 Input/Output Pins The flash memory is controlled through the input/output pins shown in table 24.2. Table 24.2 Pin Configuration Abbreviation Function Input Reset MD2, MD1 Input Set operating mode of this LSI TxD1 Output Serial transmit data output (used in boot mode) RxD1 Input Serial receive data input (used in boot mode)
Page 750: Register Descriptions
Section 24 Flash Memory 24.7 Register Descriptions The flash memory has the following registers and parameters. Table 24.3 Register Configuration Initial Data Bus Register Name Abbreviation R/W Value Address Width Flash code control status register FCCS R/W* H'80 H'FEA8 Flash program code select register FPCS H'00 H'FEA9...
Page 751 Section 24 Flash Memory There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT. The correspondence between operating modes and registers/parameters for use is shown in table 24.5. Table 24.5 Registers/Parameters and Target Modes Initiali- Program-...
Page 752: Programming/Erasing Interface Registers
Section 24 Flash Memory 24.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM.
Page 753 Section 24 Flash Memory Initial Bit Name Value Description  3 to 1 All 0 Reserved These are read-only bits and cannot be modified. (R)/W* Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR.
Page 754 Section 24 Flash Memory Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Initial Bit Name Value Description  7 to 1 All 0 Reserved These are read-only bits and cannot be modified. PPVS Program Pulse Verify Selects the programming program to be downloaded.
Page 755 Section 24 Flash Memory Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Initial Bit Name Value Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled.
Page 756 Section 24 Flash Memory Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Initial Bit Name Value Description R/W* MAT Select R/W* The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected R/W* when H'AA is written.
Page 757 Section 24 Flash Memory Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Initial Bit Name Value Description...
Page 758: Programming/Erasing Interface Parameters
Section 24 Flash Memory 24.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
Page 759 Section 24 Flash Memory (b) Initialization before Programming/Erasing The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set.
Page 760 Section 24 Flash Memory Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in On- Chip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result.
Page 761 Section 24 Flash Memory Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. Initialization before programming/erasing FPFR indicates the return value of the initialization result.
Page 762 Section 24 Flash Memory (b) Programming FPFR indicates the return value of the programming result. Initial Bit Name Value Description    Unused Returns 0.  Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1.
Page 763 Section 24 Flash Memory Initial Bit Name Value Description  Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal.
Page 764 Section 24 Flash Memory Erasure FPFR indicates the return value of the erasure result. Initial Bit Name Value Description    Unused Returns 0.  Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1.
Page 765 Section 24 Flash Memory Initial Bit Name Value Description  Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal. 1: Setting of erase block number is abnormal.
Page 766 Section 24 Flash Memory Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 25 MHz. Initial Bit Name Value Description 31 to 16 ...
Page 767 Section 24 Flash Memory Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs.
Page 768 Section 24 Flash Memory Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values range from 0 to 9 (H'00000000 to H'00000009). A value of 0 corresponds to block EB0 and a value of 9 corresponds to block EB9. Do not set a value outside the range from 0 to 9.
Page 769: On-Board Programming Mode
Section 24 Flash Memory 24.8 On-Board Programming Mode When the mode pins (MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased.
Page 770 Section 24 Flash Memory Serial Interface Setting by Host The SCI_1 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_1 to match that of the host.
Page 771 Section 24 Flash Memory State Transition Diagram The state transition after boot mode is initiated is shown in figure 24.8. (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset by boot mode) Inquiry command reception Processing of Wait for inquiry...
Page 772 Section 24 Flash Memory 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted.
Page 773: User Program Mode
Section 24 Flash Memory 24.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The programming/erasing flow is shown in figure 24.10. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state must not be made during programming/erasing.
Page 774 Section 24 Flash Memory On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on- chip program and procedure program do not overlap.
Page 775 Section 24 Flash Memory Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 24.12. Start programming procedure program Select on-chip program Disable interrupts and bus to be downloaded and master operation specify download other than CPU...
Page 776 Section 24 Flash Memory The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the on- chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data.
Page 777 Section 24 Flash Memory  To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed.  Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1.
Page 778 Section 24 Flash Memory 7. The return value in the initialization program, the FPFR parameter is determined. 8. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing.
Page 779 Section 24 Flash Memory 12. The return value in the programming program, the FPFR parameter is determined. 13. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14.
Page 780 Section 24 Flash Memory Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.13. Start erasing procedure program Select on-chip program to be downloaded and Disable interrupts and specify download bus master operation destination by FTDAR...
Page 781 Section 24 Flash Memory One erasure processing erases one block. For details on block divisions, refer to figure 24.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected.
Page 782: User Boot Mode
Section 24 Flash Memory 24.8.3 User Boot Mode This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI.
Page 783 Section 24 Flash Memory User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processing made by setting FMATS is required. However, switching back from user-MAT selection state to user-boot-MAT selection state after programming completes is impossible. Figure 24.14 shows the procedure for programming the user MAT in user boot mode.
Page 784 Section 24 Flash Memory The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 24.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background.
Page 785 Section 24 Flash Memory User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: However, switching back from user-MAT selection state to user-boot-MAT selection state after programming completes is impossible. Figure 24.15 shows the procedure for erasing the user MAT in user boot mode.
Page 786: Storable Areas For On-Chip Program And Program Data
Section 24 Flash Memory The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 24.15. MAT switching is enabled by writing a specific value to FMATS. Note, however, that while the MATs are being switched, the LSI is in an unstable state, e.g.
Page 787 Section 24 Flash Memory • Switching of the MATs by FMATS should be required when programming/erasing of the user MAT is operated in user boot mode. The program that switches the MATs should be executed from the on-chip RAM. (For details, see section 24.10, Switching between User MAT and User Boot MAT.) Make sure you know which MAT is currently selected when switching them.
Page 788 Section 24 Flash Memory Table 24.10 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-Chip RAM User MAT User MAT Storage MAT ×*   Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 789 Section 24 Flash Memory Table 24.11 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-Chip RAM User MAT User MAT Storage MAT Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 790 Section 24 Flash Memory Table 24.12 Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT Embedded On-Chip User Boot User Boot Program Item User MAT Storage MAT ×* Storage area for program data O — — — Selecting on-chip program to be downloaded Writing H'A5 to FKEY...
Page 791 Section 24 Flash Memory Table 24.13 Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT Embedded On-Chip User Boot User Boot Program Item User MAT Storage MAT Selecting on-chip program to be downloaded Writing H'A5 to FKEY ×...
Page 792: Protection
Section 24 Flash Memory 24.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection.
Page 793: Software Protection
Section 24 Flash Memory 24.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program and using the key code. Table 24.15 Software Protection Function to be Protected Programming/ Item Description Download Erasing Protection The programming/erasing protection state is...
Page 794 Section 24 Flash Memory Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100µs has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released.
Page 795: Switching Between User Mat And User Boot Mat
Section 24 Flash Memory 24.10 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing.
Page 796: Programmer Mode
Section 24 Flash Memory 24.11 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 24.16 can be used to write programs to the on-chip ROM without any limitation.
Page 797 Section 24 Flash Memory 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host.
Page 798 Section 24 Flash Memory Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state.
Page 799 Section 24 Flash Memory 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of four bytes of data. One-byte command Command or response or one-byte response...
Page 800 Section 24 Flash Memory Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command.
Page 801 Section 24 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40).
Page 802 Section 24 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code...
Page 803 Section 24 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock- mode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size...
Page 804 Section 24 Flash Memory Division Ratio Inquiry The boot program will return the supported division ratios in response to the inquiry. Command H'22 • Command, H'22, (one byte): Inquiry regarding division ratio Response H'32 Size Number of types … Number of division Division ratios ratio...
Page 805 Section 24 Flash Memory Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 • Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of...
Page 806 Section 24 Flash Memory User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 • Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Start address area Last address area …...
Page 807 Section 24 Flash Memory (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 • Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address area Last address area …...
Page 808 Section 24 Flash Memory Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 • Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 Size Number of blocks Block start address Block last address …...
Page 809 Section 24 Flash Memory (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Input frequency Number of division Division ratio...
Page 810 Section 24 Flash Memory • ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Division ratio error The ratio does not match an available ratio.
Page 811 Section 24 Flash Memory When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate.
Page 812 Section 24 Flash Memory Response H'06 • Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs and the user boot MATs have been erased by the transferred erasing program. Error Response H'C0 H'51...
Page 813 Section 24 Flash Memory 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block.
Page 814 Section 24 Flash Memory 1. Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command. After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command.
Page 815 Section 24 Flash Memory 2. Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
Page 816 Section 24 Flash Memory 3. Programming/Erasing State Information User Boot MAT Programming Selection The boot program will transfer a program for user boot MAT programming selection. The data is programmed to the user boot MATs by the transferred program for programming. Command H'42 •...
Page 817 Section 24 Flash Memory 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Address … Data … • Command, H'50, (one byte): 128-byte programming •...
Page 818 Section 24 Flash Memory Command H'50 Address • Command, H'50, (one byte): 128-byte programming • Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Page 819 Section 24 Flash Memory Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number • Command, H'58, (one byte): Erasure • Size (one byte): The number of bytes that represents the erase block number This is fixed to 1.
Page 820 Section 24 Flash Memory Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size • Command: H'52 (one byte): Memory read • Size (one byte): Amount of data that represents the area, read address, and read size (fixed at •...
Page 821 Section 24 Flash Memory User-Program Check Sum The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B • Command, H'4B, (one byte): Check sum for user program Response H'5B Size Checksum of user program •...
Page 822 Section 24 Flash Memory Boot Program Status Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (one byte): Inquiry regarding boot program's state Response H'5F...
Page 823 Section 24 Flash Memory Table 24.20 Error Codes Code Description H'00 No error H'11 Check sum error H'12 Program size error H'21 Device code mismatch error H'22 Clock mode mismatch error H'24 Bit rate selection error H'25 Input frequency error H'26 Division ratio error H'27...
Page 824: Usage Notes
Section 24 Flash Memory 24.13 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating.
Page 825 Section 24 Flash Memory 12. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 200 µs at the maximum.
Page 826 Section 24 Flash Memory Rev. 1.00 May 09, 2008 Page 800 of 954 REJ09B0462-0100...
Page 827: Section 25 Clock Pulse Generator
Section 25 Clock Pulse Generator Section 25 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, subclock input circuit, and subclock waveform forming circuit.
Page 828: Oscillator
Section 25 Clock Pulse Generator 25.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 25.1.1 Connecting Crystal Resonator Figure 25.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance R , given in table 25.1 should be used.
Page 829: External Clock Input Method
Section 25 Clock Pulse Generator Table 25.2 Crystal Resonator Parameters Frequency (MHz) (max) (Ω) (max) (pF) 25.1.2 External Clock Input Method Figure 25.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode or watch mode.
Page 830 Section 25 Clock Pulse Generator Table 25.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item Symbol Min. Max. Unit Test Conditions  External clock input pulse Figure 25.5 width low level  External clock input pulse width high level ...
Page 831: Duty Correction Circuit
Section 25 Clock Pulse Generator 3.0 V EXTAL φ (Internal and external) DEXT ) includes a RES pulse width (t Note: * The external clock output stabilization delay time (t DEXT RESW Figure 25.6 Timing of External Clock Output Stabilization Delay Time 25.2 Duty Correction Circuit The duty correction circuit generates the system clock (φ) by correcting the duty of the clock...
Page 832: Subclock Input Circuit
Section 25 Clock Pulse Generator 25.3 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin. Figure 25.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin. When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the pin to 0.
Page 833: Subclock Waveform Forming Circuit
Section 25 Clock Pulse Generator EXCLH EXCLL × 0.5 EXCL EXCLr EXCLf Figure 25.8 Subclock Input Timing 25.4 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided φ clock. The sampling frequency is set by the NESEL bit in LPWRCR.
Page 834: Usage Notes
Section 25 Clock Pulse Generator 25.6 Usage Notes 25.6.1 Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user.
Page 835: Section 26 Power-Down Modes
Section 26 Power-Down Modes Section 26 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has four power-down operating modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Page 836: Register Descriptions
Section 26 Power-Down Modes 26.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Page 837 Section 26 Power-Down Modes Initial Bit Name Value Description STS2 Standby Timer Select 2 to 0 STS1 On canceling software standby mode or watch mode, these bits select the wait time for clock stabilization STS0 from clock oscillation start. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency.
Page 838 Section 26 Power-Down Modes Table 26.2 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 25 MHz 10 MHz 8 MHz Unit 8192 states 16384 states 32768 states 65536 states 131072 states 13.1 16.4 262144 states 10.4 26.2 32.8 ...
Page 839: Low-Power Control Register (Lpwrcr)
Section 26 Power-Down Modes 26.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Initial Bit Name Value Description DTON Direct Transfer On Flag The initial value should not be changed. LSON Low-Speed On Flag The initial value should not be changed. NESEL Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (φSUB)
Page 840: Module Stop Control Registers H, L, A, And B (Mstpcrh, Mstpcrl, Mstpcra, Mstpcrb)
Section 26 Power-Down Modes 26.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. •...
Page 841 Section 26 Power-Down Modes • MSTPCRL Bit Name Initial Value R/W Corresponding Module MSTP7 Reserved The initial value should not be changed. MSTP6 Serial communication interface_1 (SCI_1) MSTP5 Reserved The initial value should not be changed. MSTP4 C bus interface channel_0 (IIC_0/SMBUS) MSTP3 Reserved The initial value should not be changed.
Page 842 Section 26 Power-Down Modes • MSTPCRB Bit Name Initial Value R/W Corresponding Module MSTPB7 1 Reserved The initial value should not be changed. MSTPB6 1 Reserved The initial value should not be changed. MSTPB5 1 Reserved The initial value should not be changed. MSTPB4 1 C bus interface_2 (IIC_2) MSTPB3 1...
Page 843: Mode Transitions And Lsi States
Section 26 Power-Down Modes 26.2 Mode Transitions and LSI States Figure 26.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The reset input causes a mode transition from any state to the reset state.
Page 844 Section 26 Power-Down Modes Table 26.3 LSI Internal States in Each Operating Mode Software Function High Speed Medium Speed Sleep Module Stop Watch Standby System clock pulse Functioning Functioning Functioning Functioning Stopped Stopped generator Subclock input Functioning Functioning Functioning Functioning Functioning Stopped Instruction...
Page 845: Medium-Speed Mode
Section 26 Power-Down Modes 26.3 Medium-Speed Mode The operating mode changes to medium-speed mode as soon as the current bus cycle ends by the settings of the SCK2 to SCK0 bits in SBYCR. The operating clock can be selected from φ/2, φ/4, φ/8, φ/16, or φ/32.
Page 846: Sleep Mode
Section 26 Power-Down Modes 26.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not.
Page 847: Software Standby Mode
Section 26 Power-Down Modes 26.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0.
Page 848 Section 26 Power-Down Modes Oscillator φ NMIEG SSBY Software standby mode NMI exception NMI exception (power-down mode) handling handling NMIEG = 1 SSBY = 1 Oscillation SLEEP instruction stabilization time t OSC2 Figure 26.3 Software Standby Mode Application Example Rev. 1.00 May 09, 2008 Page 822 of 954 REJ09B0462-0100...
Page 849: Watch Mode
Section 26 Power-Down Modes 26.6 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
Page 850: Module Stop Mode
Section 26 Power-Down Modes 26.7 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle.
Page 851: Section 27 List Of Registers
Section 27 List of Registers Section 27 List of Registers The list of registers gives information on the on-chip register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module.
Page 852 Section 27 List of Registers 5. Register addresses (classification by type of module) • The register addresses are described by modules. • The register addresses are described in channel order when the module has multiple channels. Rev. 1.00 May 09, 2008 Page 826 of 954 REJ09B0462-0100...
Page 853: Register Addresses (Address Order)
Section 27 List of Registers 27.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits. The number of access states indicates the number of states based on the specified reference clock. Number Data Access Register Name Abbreviation of bits Address...
Page 854 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port 4 noise canceler enable P4NCE H'F91B PORT register Port 4 noise canceler decision P4NCMC H'F91D PORT control register Port 4 noise cancel cycle setting P4NCCS H'F91F PORT...
Page 855 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port 9 data register P9DR H'F942 PORT (PORTS = 1) Port 9 input data register P9PIN H'F944 (Read) PORT (PORTS = 1) Port 9 pull-up MOS control P9PCR H'F946 PORT...
Page 856 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port C Nch-OD control register PCNOCR H'F968 PORT (PORTS = 1) Port D Nch-OD control register PDNOCR H'F969 PORT (PORTS = 1) Port C noise canceler enable PCNCE H'F96A PORT...
Page 857 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port G Nch-OD control register PGNOCR H'F988 PORT (PORTS = 1) Port H Nch-OD control register PHNOCR H'F989 PORT (PORTS = 1) Port G noise canceler enable PGNCE H'F98A PORT...
Page 858 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Repeat header maximum low-level RMAX H'FA51 period register Reset status register RSTSR H'FB35 SYSTEM 8 TCM timer counter register_0 TCMCNT_0 H'FBC0 TCM_0 TCM timer cycle upper limit TCMMLCM_0 H'FBC2 TCM_0...
Page 859 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States A/D data register A ADDRA H'FC00 converter A/D data register B ADDRB H'FC02 converter A/D data register C ADDRC H'FC04 converter A/D data register D ADDRD H'FC06 converter...
Page 860 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States FSI access host base address FSIHBARH H'FC50 register H FSI access host base address FSIHBARL H'FC51 register L FSI flash memory size register FSISR H'FC52 FSI command host base address...
Page 861 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States FSI write data register LH FSIWDRLH H'FC6C FSI write data register LL FSIWDRLL H'FC6D FSILPC command status register 2 FSILSTR2 H'FC6E FSI control register 1 FSICR1 H'FC90 FSI control register 2...
Page 862 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States PWMPRE4_A H'FD09 PWMU_A 8 PWM prescaler register 4_A PWMREG5_A 8 H'FD0A PWMU_A 8 PWM duty setting register 5_A PWMPRE5_A H'FD0B PWMU_A 8 PWM prescaler register 5_A PWM clock control register_A PWMCKCR_A 8 H'FD0C...
Page 863 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Timer counter _1 TCNT_1 H'FD46 TPU_1 Timer general register A_1 TGRA_1 H'FD48 TPU_1 Timer general register B_1 TGRB_1 H'FD4A TPU_1 PEC operation data input register PECX H'FD60 SMBUS...
Page 864 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port C noise cancel cycle setting PCNCCS H'FE05 PORT register (PORTS = 0) Port G noise canceler enable PGNCE H'FE06 PORT register (PORTS = 0) Port G noise canceler decision PGNCMC H'FE07...
Page 865 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Bidirectional data register 3 TWR3 H'FE23 Bidirectional data register 4 TWR4 H'FE24 Bidirectional data register 5 TWR5 H'FE25 Bidirectional data register 6 TWR6 H'FE26 Bidirectional data register 7 TWR7...
Page 866 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Host interface control register 2 HICR2 H'FE42 Host interface control register 3 HICR3 H'FE43 Wakeup event interrupt mask WUEMRB H'FE44 register B Wakeup event interrupt mask WUEMRA H'FE45 register A...
Page 867 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port D input data register PDPIN H'FE4F PORT (Read) (PORTS = 0) Port D data direction register PDDDR H'FE4F PORT (Write) (PORTS = 0) Timer control register_0 TCR_0 H'FE50...
Page 868 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Keyboard matrix interrupt register KMIMRA H'FE83 (RELOCATE = 1) Wake-up sense control register A WUESCRA H'FE84 Wake-up input interrupt status WUESRA H'FE85 register A Wake-up enable register WUEER H'FE86...
Page 869 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Keyboard data buffer transmit data KBTR_0 H'FEC1 PS2_0 register_0 Keyboard control register 1_1 KBCR1_1 H'FEC2 PS2_1 Keyboard data buffer transmit data KBTR_1 H'FEC3 PS2_1 register_1 Timer XY control register...
Page 870 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States IRQ sense control register L ISCRL H'FEED Address break control register ABRKCR H'FEF4 Break address register A BARA H'FEF5 Break address register B BARB H'FEF6 Break address register C...
Page 871 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port A data direction register PADDR H'FFAB (Write) PORT (PORTS = 0) Port 1 pull-up MOS control register P1PCR H'FFAC PORT (PORTS = 0) Port 2 pull-up MOS control register P2PCR H'FFAD...
Page 872 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Port B input data register PBPIN H'FFBD (Read) PORT (PORTS = 0) Port 7 input data register P7PIN H'FFBE (Read) PORT (PORTS = 0) Port B data direction register PBDDR H'FFBE (Write)
Page 873 Section 27 List of Registers Number Data Access Register Name Abbreviation of bits Address Module Width States Slave address register_0 SAR_0 H'FFDF IIC_0 Timer control/status register TCSR_1 H'FFEA (Write) WDT_1 Timer control/status register TCSR_1 H'FFEA (Read) WDT_1 Timer counter _1 TCNT_1 H'FFEA (Write) WDT_1...
Page 874: Register Bits
Section 27 List of Registers 27.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 875 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCMICRF_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TCM_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ...
Page 876 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCMIER_2 OVIE MAXOVIE CMIE TCMIPE ICPIE MINUDIE CMMS TCM_2 TCMMINCM_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 877 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module    FMCR LOOP OUT2 OUT1 SCIF BACK FLSR TEMT THRE RXFIFOERR FMSR DDCD TERI DDSR DCTS FSCR...
Page 878 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FSIARH bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 FSIARM bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 FSIARL...
Page 879 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PWMU_A PWMPRE3_A bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PWMREG4_A bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...
Page 880 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module    TSR_1 TCFD TCFU TCFV TGFB TGFA TPU_1 TCNT_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 881 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT PCNCE PC7NCE PC6NCE PC5NCE PC4NCE PC3NCE PC2NCE PC1NCE PC0NCE PCNCMC PC7NCMC PC6NCMC PC5NCMC PC4NCMC PC3NCMC PC2NCMC PC1NCMC PC0NCMC ...
Page 882 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TWR10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TWR11 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TWR12...
Page 883 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PGODR PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR PORT PGPIN PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN...
Page 884 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2     TMDR_2 TIOR_2 IOB3 IOB2 IOB1...
Page 885 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module       FCCS FLER        FPCS PPVS ...
Page 886 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module WUESCRB WUE7SC WUE6SC WUE5SC WUE4SC WUE3SC WUE2SC WUE1SC WUE0SC WUESRB WUE7F WUE6F WUE5F WUE4F WUE3F WUE2F WUE1F WUE0F ICRA...
Page 887 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RDR_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCI_1      SCMR_1 SDIR SINV SMIF...
Page 888 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR PORT P9DR P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR...
Page 889 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_X TCSR_X CMFB CMFA TICRR bit7 bit6 bit5 bit4 bit3...
Page 890: Register States In Each Operating Mode
Section 27 List of Registers 27.3 Register States in Each Operating Mode Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      CCR1 Initialized      CCR2 Initialized  ...
Page 891 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      TCMICRF_1 Initialized TCM_1      TCMCSR_1 Initialized      TCMCR_1 Initialized ...
Page 892 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      SCIF Initialized FLCR      Initialized FMCR      Initialized FLSR ...
Page 893 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      Initialized FSIARH      Initialized FSIARM      Initialized FSIARL  ...
Page 894 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module   PWMU_A PWMPRE3_A Initialized Initialized Initialized Initialized   PWMREG4_A Initialized Initialized Initialized Initialized   PWMPRE4_A Initialized Initialized Initialized Initialized ...
Page 895 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      TPU_1 TCNT_1 Initialized      TGRA_1 Initialized      TGRB_1 Initialized ...
Page 896 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      PORT PGNCMC Initialized      PGNCCS Initialized      PHPIN Initialized ...
Page 897 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      TWR15 Initialized      IDR3 Initialized      ODR3 Initialized  ...
Page 898 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      PORT PCODR Initialized      PDODR Initialized       PCPIN ...
Page 899 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      KMIMRA Initialized      WUESCRA Initialized      WUESRA Initialized  ...
Page 900 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      TCNT_Y Initialized TMR_Y      ICXR_0 Initialized IIC_0      KBCRH_0 Initialized PS2_0 ...
Page 901 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      SYSTEM LPWRCR Initialized      MSTPCRH Initialized      MSTPCRL Initialized ...
Page 902 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      PORT PBODR Initialized       PBPIN      P8DDR Initialized ...
Page 903 Section 27 List of Registers Register High-Speed/ Module Software Abbreviation Reset Medium speed Watch Sleep Stop Standby Module      WDT_1 TCSR_1 Initialized      TCNT_1 Initialized      TCR_X Initialized TMR_X ...
Page 904: Register Selection Condition
Section 27 List of Registers 27.4 Register Selection Condition Lower Address Register Abbreviation Register Selection Condition Module H'F900 P1DDR PORTS = 1 PORT H'F901 P2DDR H'F902 P1DR H'F903 P2DR H'F904 P1PIN (Read) H'F905 P2PIN (Read) H'F906 P1PCR H'F907 P2PCR H'F910 P3DDR H'F911 P4DDR...
Page 905 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'F92B PORTS = 1 PORT P6NCE H'F92D P6NCMC H'F92F P6NCCS H'F931 P8DDR H'F933 P8DR H'F934 P7PIN (Read) H'F935 P8PIN (Read) H'F940 P9DDR H'F942 P9DR H'F944 P9PIN (Read) H'F946 P9PCR H'F950...
Page 906 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'F96E PORTS = 1 PORT PCNCCS H'F971 PFDDR H'F973 PFODR H'F974 PEPIN (Read) H'F975 PFPIN (Read) H'F977 PFPCR H'F979 PFNOCR H'F980 PGDDR H'F981 PHDDR H'F982 PGODR H'F983 PHODR H'F984 PGPIN (Read)
Page 907 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FA4D MSTPA3 = 0 DT0MAX H'FA4E DT1MIN H'FA4F DT1MAX H'FA50 RMIN H'FA51 RMAX H'FB35 RSTSR No condition SYSTEM H'FBC0 TCMCNT_0 MSTPB1 = 0 TCM_0 H'FBC2 TCMMLCM_0 H'FBC4 TCMICR_0 H'FBC6 TCMICRF_0...
Page 908 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module MSTP9 = 0 A/D converter H'FC00 ADDRA H'FC02 ADDRB H'FC04 ADDRC H'FC06 ADDRD H'FC08 ADDRE H'FC0A ADDRF H'FC0C ADDRG H'FC0E ADDRH H'FC10 ADCSR H'FC11 ADCR H'FC50 FSIHBARH MSTP0 = 0 MSTPA2 = 0 H'FC51...
Page 909 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module MSTP0 = 0 H'FC64 FSIGPRE MSTPA2 = 0 H'FC65 FSIGPRF H'FC66 SLCR H'FC67 FSIARH H'FC68 FSIARM H'FC69 FSIARL H'FC6A FSIWDRHH H'FC6B FSIWDRHL H'FC6C FSIWDRLH H'FC6D FSIWDRLL H'FC6E FSILSTR2 H'FC90 FSICR1...
Page 910 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module MSTPB3 = 0 SCIF H'FC20 FRBR H'FC20 FTHR H'FC20 FDLL H'FC21 FIER H'FC21 FDLH H'FC22 FIIR H'FC22 FFCR H'FC23 FLCR H'FC24 FMCR H'FC25 FLSR H'FC26 FMSR H'FC27 FSCR H'FC28 SCIFCR...
Page 911 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FD0D PWMOUTCR_A MSTPB0 = 0 PWMU_A H'FD0E PWMMDCR_A H'FD0F PWMPCR_A H'FD10 PWMREG0_B MSTPB0 = 0 PWMU_B H'FD11 PWMPRE0_B H'FD12 PWMREG1_B H'FD13 PWMPRE1_B H'FD14 PWMREG2_B H'FD15 PWMPRE2_B H'FD16 PWMREG3_B H'FD17 PWMPRE3_B...
Page 912 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FDC0 LADR1H MSTP0 = 0 H'FDC1 LADR1L H'FDC2 LADR2H H'FDC3 LADR2L H'FDC4 SCIFADRH H'FDC5 SCIFADRL H'FDD4 LADR4H H'FDD5 LADR4L H'FDD6 IDR4 H'FDD7 ODR4 H'FDD8 STR4 H'FDD9 HICR4 H'FDDA SIRQCR2 H'FDDB...
Page 913 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE10 PTCNT0 No condition PORT H'FE11 PTCNT1 H'FE12 PTCNT2 H'FE14 P9PCR PORTS = 0 H'FE16 PGNOCR H'FE19 PFNOCR H'FE1C PCNOCR H'FE1D PDNOCR H'FE20 TWR0MW MSTP0 = 0 TWR0SW H'FE21 TWR1...
Page 914 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE35 LADR3L MSTP0 = 0 H'FE36 SIRQCR0 H'FE37 SIRQCR1 H'FE38 IDR1 H'FE39 ODR1 H'FE3A STR1 H'FE3B SIRQCR4 H'FE3C IDR2 H'FE3D ODR2 H'FE3E STR2 H'FE3F HISEL H'FE40 HICR0 H'FE41 HICR1 H'FE42...
Page 915 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE50 TCR_0 MSTP1 = 0 TPU_0 H'FE51 TMDR_0 H'FE52 TIORH_0 H'FE53 TIORL_0 H'FE54 TIER_0 MSTP1 = 0 TPU_0 H'FE55 TSR_0 H'FE56 TCNT_0 H'FE58 TGRA_0 H'FE5A TGRB_0 H'FE5C TGRC_0 H'FE5E TGRD_0...
Page 916 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE88 ICCR_2 MSTPB4 = 0 IIC_2 H'FE89 ICSR_2 H'FE8A ICRES_2 H'FE8C ICXR_2 H'FE8E ICDR_2 ICE in ICCR_2 = 1 H'FE8E SARX_2 ICE in ICCR_2 = 0 H'FE8F ICMR_2 ICE in ICCR_2 = 1 H'FE8F...
Page 917 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FED8 KBCRH_0 MSTP2 = 0 H'FED9 KBCRL_0 H'FEDA KBBR_0 H'FEDB KBCR2_0 H'FEDC KBCRH_1 H'FEDD KBCRL_1 H'FEDE KBBR_1 H'FEDF KBCR2_1 H'FEE6 ICRES_0 MSTP4 = 0, IICE in STCR = 1 IIC_0 H'FEE8 ICRA...
Page 918 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FF86 MSTPCRH RELOCATE = 0, SYSTEM FLSHE in STCR = 0 MSTPCRH RELOCATE = 1 H'FF87 MSTPCRL RELOCATE = 0, FLSHE in STCR = 0 MSTPCRL RELOCATE = 1 H'FF88 SMR_1 MSTP6 = 0...
Page 919 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFB1 P2DDR PORTS = 0 PORT H'FFB2 P1DR H'FFB3 P2DR H'FFB4 P3DDR H'FFB5 P4DDR H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR H'FFBD P8DDR (Write)
Page 920 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFCD TCORA_1 MSTP12 = 0 TMR_0, TMR_1 H'FFCE TCORB_0 H'FFCF TCORB_1 H'FFD0 TCNT_0 H'FFD1 TCNT_1 H'FFD8 ICCR_0 MSTP4 = 0, RELOCATE = 0 IIC_0 IICE in STCR = 1 ICCR_0 MSTP4 = 0, RELOCATE = 1 H'FFD9...
Page 921 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFF0 TCR_X MSTP8 = 0, RELOCATE = 1 TMR_X TCR_X MSTP8 = 0, TMRX/Y in RELOCATE = 0 TCONRS = 0 KINWUE in SYSCR TCR_Y TMRX/Y in TMR_Y TCONRS = 1 H'FFF1...
Page 922 Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFF6 TCORA_X MSTP8 = 0, RELOCATE = 1 TMR_X TCORA_X MSTP8 = 0, RELOCATE = 0 KINWUE in SYSCR = 0 TMRX/Y in TCONRS = 0 H'FFF7 TCORB_X MSTP8 = 0, RELOCATE = 1 TMR_X...
Page 923: Register Addresses (Classification By Type Of Module)
Section 27 List of Registers 27.5 Register Addresses (Classification by Type of Module) Register Number Data Bus Access Module Abbreviation of Bits Address Width States WUEMRB H'FE44 WUEMRA H'FE45 KMIMRB H'FE81 (RELOCATE = 1) KMIMRA H'FE83 (RELOCATE = 1) WUESCRA H'FE84 WUESRA H'FE85...
Page 924 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States H'FFC2 KMIMRA H'FFF3 (RELOCATE = 0) H'FFC6 WSCR H'FFC7 PORT P1DDR H'F900 (PORTS = 1) PORT P2DDR H'F901 (PORTS = 1) PORT P1DR H'F902 (PORTS = 1) PORT P2DR...
Page 925 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PORT P5PIN H'F924 (Read) (PORTS = 1) PORT P6PCR H'F927 (PORTS = 1, RELOCATE = 0) PORT P6PIN H'F925 (Read) (PORTS = 1) PORT P6NCE H'F92B (PORTS = 1)
Page 926 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PORT PDODR H'F963 (PORTS = 1) PORT PCPIN H'F964 (Read) (PORTS = 1) PORT PDPIN H'F965 (Read) (PORTS = 1) PORT PCPCR H'F966 (PORTS = 1) PORT PDPCR H'F967 (PORTS = 1)
Page 927 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PORT PGNCE H'F98A (PORTS = 1) PORT PGNCMC H'F98C (PORTS = 1) PORT PGNCCS H'F98E (PORTS = 1) PORT P6NCE H'FE00 (PORTS = 0) PORT P6NCMC H'FE01 (PORTS = 0)
Page 928 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PORT PFODR H'FE49 (PORTS = 0) PORT PEPIN H'FE4A (Read) (write prohibited) (PORTS = 0) PORT PFPIN H'FE4B (Read) (PORTS = 0) PORT PFDDR H'FE4B (Write) (PORTS = 0)
Page 929 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PORT P4DDR H'FFB5 (PORTS = 0) PORT P3DR H'FFB6 (PORTS = 0) PORT P4DR H'FFB7 (PORTS = 0) PORT P5DDR H'FFB8 (PORTS = 0) PORT P6DDR H'FFB9 (PORTS = 0)
Page 930 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States DT0MIN H'FA4C DT0MAX H'FA4D DT1MIN H'FA4E DT1MAX H'FA4F RMIN H'FA50 RMAX H'FA50 TCM_0 TCMCNT_0 H'FBC0 TCM_0 TCMMLCM_0 H'FBC2 TCM_0 TCMICR_0 H'FBC4 TCM_0 TCMICRF_0 H'FBC6 TCM_0 TCMCSR_0...
Page 931 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States FSIHBARH H'FC50 FSIHBARL H'FC51 FSISR H'FC52 CMDHBARH H'FC53 CMDHBARH H'FC54 FSICMDR H'FC55 FSILSTR1 H'FC56 FSIGPR1 H'FC57 FSIGPR2 H'FC58 FSIGPR3 H'FC59 FSIGPR4 H'FC5A FSIGPR5 H'FC5B FSIGPR6 H'FC5C...
Page 932 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States FSILSTR2 H'FC6E FSICR1 H'FC90 FSICR2 H'FC91 FSIBNR H'FC92 FSINS H'FC93 FSIRDINS H'FC94 FSIPPINS H'FC95 FSISTR H'FC96 FSITDR0 H'FC98 FSITDR1 H'FC99 FSITDR2 H'FC9A FSITDR3 H'FC9B FSITDR4 H'FC9C...
Page 933 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PWMU_A PWMOUTCR_A H'FD0D PWMU_A PWMMDCR_A H'FD0E PWMU_A PWMPCR_A H'FD0F PWMU_B PWMREG0_B H'FD10 PWMU_B PWMPRE0_B H'FD11 PWMU_B PWMREG1_B H'FD12 PWMU_B PWMPRE1_B H'FD13 PWMU_B PWMREG2_B H'FD14 PWMU_B PWMPRE2_B...
Page 934 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States TPU_1 TCR_1 H'FD40 TPU_1 TMDR_1 H'FD41 TPU_1 TIOR_1 H'FD42 TPU_1 TIER_1 H'FD44 TPU_1 TSR_1 H'FD45 TPU_1 TCNT_1 H'FD46 TPU_1 TGRA_1 H'FD48 TPU_1 TGRB_1 H'FD4A TPU_2 TCR_2...
Page 935 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States TMR_X TCR_X H'FFF0 TMR_X TCSR_X H'FFF1 TMR_X TICRR H'FFF2 TMR_X TICRF H'FFF3 TMR_X TCNT_X H'FFF4 TMR_X TCORC H'FFF5 TMR_X TCORA_X H'FFF6 TMR_X TCORB_X H'FFF7 TMR_X TCONRI...
Page 936 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States WDT_1 TCNT_1 H'FFEA (Write) WDT_1 TCNT_1 H'FFEB (Read) SCI_1 SMR_1 H'FF88 SCI_1 BRR_1 H'FF89 SCI_1 SCR_1 H'FF8A SCI_1 TDR_1 H'FF8B SCI_1 SSR_1 H'FF8C SCI_1 RDR_1 H'FF8D...
Page 937 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States PS2_0 KBBR_0 H'FEDA PS2_0 KBCR2_0 H'FEDB PS2_1 KBCR1_1 H'FEC2 PS2_1 KBTR_1 H'FEC3 PS2_1 KBCRH_1 H'FEDC PS2_1 KBCRL_1 H'FEDD PS2_1 KBBR_1 H'FEDE PS2_1 KBCR2_1 H'FEDF LADR1H H'FDC0...
Page 938 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States TWR6 H'FE26 TWR7 H'FE27 TWR8 H'FE28 TWR9 H'FE29 TWR10 H'FE2A TWR11 H'FE2B TWR12 H'FE2C TWR13 H'FE2D TWR14 H'FE2E TWR15 H'FE2F IDR3 H'FE30 ODR3 H'FE31 STR3 H'FE32...
Page 939 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States HICR2 H'FE42 HICR3 H'FE43 A/D converter ADDRA H'FC00 A/D converter ADDRB H'FC02 A/D converter ADDRC H'FC04 A/D converter ADDRD H'FC06 A/D converter ADDRE H'FC08 A/D converter ADDRF...
Page 940 Section 27 List of Registers Register Number Data Bus Access Module Abbreviation of Bits Address Width States FECS H'FEAA FKEY H'FEAC FMATS H'FEAD FTDAR H'FEAE SYSTEM RSTSR H'FB35 SYSTEM SYSCR3 H'FE7D SYSTEM MSTPCRA H'FE7E SYSTEM MSTPCRB H'FE7F SYSTEM SBYCR H'FF84 SYSTEM LPWRCR H'FF85...
Page 941: Section 28 Electrical Characteristics
Section 28 Electrical Characteristics Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 lists the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* –0.3 to +4.3 Input voltage (except ports 7, D, A, G, PE4, –0.3 to V + 0.3 PE2 to PE0, P97, and P52)
Page 942: Dc Characteristics
Section 28 Electrical Characteristics 28.2 DC Characteristics Table 28.2 lists the DC characteristics. Table 28.3 lists the permissible output currents. Table 28.4 lists the bus drive characteristics. Table 28.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV...
Page 943 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV = 0 V Test Item Symbol Min. Typ. Max.
Page 944 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref* = 3.0 V to AV = AV = 0 V Item Symbol Min. Typ. Max. Unit Test Conditions ...
Page 945 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (3) Using LPC Function Conditions: V = 3.0 V to 3.6 V, V = 0 V Test Item Symbol Min. Max. Unit Conditions × 0.5  Input high voltage P37 to P30, P82 to P80, PB1, PB0 ...
Page 946 Section 28 Electrical Characteristics Table 28.3 Permissible Output Currents Conditions: V = 3.0 V to 3.6 V, V = 0V Item Symbol Min. Typ. Max. Unit   Permissible output low SCL0, SDA0, SCLA to SCLD, current (per pin) SDAA to SDAD, PS2AC to PS2BC, PS2AD to PS2BD, and PA7 to PA4 (bus drive function selected)
Page 947 Section 28 Electrical Characteristics Table 28.4 Bus Drive Characteristics Conditions: V = 3.0 V to 3.6V, V = 0 V Applicable pins: SCL0, SDA0, SCLA to SCLD, and SDAA to SDAD (bus drive function selected) Item Symbol Min. Typ. Max. Unit Test Conditions ×...
Page 948 Section 28 Electrical Characteristics This LSI 2 kΩ Port Darlington transistor Figure 28.1 Darlington Transistor Drive Circuit (Example) This LSI 600 Ω Ports 1 to 3, C and D Figure 28.2 LED Drive Circuit (Example) Rev. 1.00 May 09, 2008 Page 922 of 954 REJ09B0462-0100...
Page 949: Ac Characteristics
Section 28 Electrical Characteristics 28.3 AC Characteristics Figure 28.3 shows the test conditions for the AC characteristics. C = 30pF : All ports = 2.4 kΩ = 12 kΩ I/O timing test levels LSI output pin • Low level : 0.8 V •...
Page 950 Section 28 Electrical Characteristics Table 28.5 Clock Timing = 0 V, φ = 8 MHz to 10 MHz Condition A: = 3.0 V to 3.6 V, V = 0 V, φ = 10 MHz to 25 MHz Condition B: = 3.0 V to 3.6 V, V Condition A Condition B Item...
Page 951 Section 28 Electrical Characteristics EXTAL DEXT OSC1 φ Figure 28.5 Oscillation Stabilization Timing φ IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) WUEi ( i = 1 to 15 ) OSC2 PS2AC to PS2BC Figure 28.6 Oscillation Stabilization Timing (Returning from Software Standby Mode) Rev.
Page 952: Control Signal Timing
Section 28 Electrical Characteristics 28.3.2 Control Signal Timing Table 28.6 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, PS2A, and PS2B can be operated based on the subclock (φ = 32.768 kHz).
Page 953 Section 28 Electrical Characteristics φ RESS RESS RESW Figure 28.7 Reset Input Timing φ NMIS NMIH NMIW IRQi (i = 0 to 15) IRQW IRQS IRQH Edge input IRQS Level input IRQS IRQH KINi (i = 0 to 15) WUEi IRQW (i = 0 to 15) Figure 28.8 Interrupt Input Timing...
Page 954: Timing Of On-Chip Peripheral Modules
Section 28 Electrical Characteristics 28.3.3 Timing of On-Chip Peripheral Modules Tables 28.7 to 28.9 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, and PC2A to PC2B) and watchdog timer (WDT_1) only.
Page 955 Section 28 Electrical Characteristics Test Item Symbol Min. Max. Unit Conditions  Input clock rise time Figure 28.18 SCKr  Input clock fall time SCKf  Transmit data delay time (synchronous) Figure 28.19  Receive data setup time (synchronous)  Receive data hold time (synchronous) ...
Page 956 Section 28 Electrical Characteristics φ TOCD Output compare outputs* TICS Input capture inputs* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0 Figure 28.10 TPU Input/Output Timing φ TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 28.11 TPU Clock Input Timing φ...
Page 957 Section 28 Electrical Characteristics φ TMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 28.14 8-Bit Timer Reset Input Timing φ TCMS TCMCYI TCMMCI Figure 28.15 TCM Input Setup Time φ TCMCKS TCMCKI TCMCKW TCMCKW Figure 28.16 TCM Clock Input Timing φ PWOD PWMU5A to PWMU0A, PWMU5B to PWMU0B Figure 28.17 PWMU, PWMX Output Timing...
Page 958 Section 28 Electrical Characteristics SCK1 TxD1 (transmit data) RxD1 (receive data) Figure 28.19 SCI Input/Output Timing (Clock Synchronous Mode) FSICK FSICK FSISS FSIDO FSIDI Figure 28.20 FSI Input/Output Timing Rev. 1.00 May 09, 2008 Page 932 of 954 REJ09B0462-0100...
Page 959 Section 28 Electrical Characteristics Table 28.8 PS2 Timing = 0 V, φ = 8 MHz to maximum operating frequency Conditions: = 3.0 V to 3.6 V, V Standard Value Test Conditions Remarks Item Symbol Min. Typ. Max. Unit   KCLK, KD output fall time Figure 28.21...
Page 960 Section 28 Electrical Characteristics Table 28.9 I C Bus Timing = 0 V, φ = 8 MHz to maximum operating frequency Conditions: = 3.0 V to 3.6 V, V Test Item Symbol Min. Typ. Max. Unit Conditions   SCL input cycle time Figure 28.22 ...
Page 961 Section 28 Electrical Characteristics Table 28.10 LPC Timing = 0 V, φ = 8 MHz to maximum operating frequency Conditions: = 3.0 V to 3.6V, V Test Item Symbol Min. Typ. Max. Unit Conditions   Input clock cycle Figure Lcyc 28.23 ...
Page 962 Section 28 Electrical Characteristics Test voltage: 0.4Vcc 50 pF Figure 28.24 Test Conditions for Tester Table 28.11 JTAG Timing = 0 V, φ = 8 MHz to maximum operating frequency Conditions: = 3.0 V to 3.6 V, V Test Item Symbol Min.
Page 963 Section 28 Electrical Characteristics ETCK RSTHW ETRST TRSTW Figure 28.26 Reset Hold Timing ETCK TMSS TMSH ETMS TDIS TDIH ETDI TDOD ETDO Figure 28.27 JTAG Input/Output Timing Rev. 1.00 May 09, 2008 Page 937 of 954 REJ09B0462-0100...
Page 964: A/D Conversion Characteristics
Section 28 Electrical Characteristics 28.4 A/D Conversion Characteristics Table 28.12 lists the A/D conversion characteristics. Table 28.12 A/D Conversion Characteristics (AN11 to AN0 Input) Conditions: = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, AVref = 3.0 V to AV = 0 V, φ...
Page 965: Flash Memory Characteristics
Section 28 Electrical Characteristics 28.5 Flash Memory Characteristics Table 28.13 lists the flash memory characteristics. Table 28.13 Flash Memory Characteristics Conditions: = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, Avref = 3.0 V to AV = AV = 0 V Ta = 0°C to +75°C (operating temperature range for programming/erasing)
Page 966: Power-On Reset Characteristics
Section 28 Electrical Characteristics 28.6 Power-on Reset Characteristics Table 28.14 lists the power-on reset characteristics. Table 28.14 Electrical Characteristics of the Power-on Reset Circuit Conditions: = 3.0 V to 3.6 V, V = 0 V Test Item Symbol Min. Typ. Max.
Page 967: Usage Notes
Section 28 Electrical Characteristics 28.7 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin, and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 28.29.
Page 968 Section 28 Electrical Characteristics Rev. 1.00 May 09, 2008 Page 942 of 954 REJ09B0462-0100...
Page 969: Appendix
Appendix Appendix I/O Port States in Each Pin State Table A.1 I/O Port States in Each Pin State Port Name Software Program Pin Name Reset Standby Mode Watch Mode Sleep Mode Execution State Port 1 keep keep keep I/O port Port 2 keep keep...
Page 970: Product Lineup
Appendix Product Lineup Product Type Part No. Mark Code Package (Code) H8S/2112R Flash memory R4F2112R F2112RTE25V PTQP0144LC-A (TFP-144V) version F2112RBG25V PLBG0176GA-A (BP-176V) F2112RLP25V PTLG0145JB-A (TLP-145V) Rev. 1.00 May 09, 2008 Page 944 of 954 REJ09B0462-0100...
Page 971: Package Dimensions
Appendix Package Dimensions Figure C.1 Package Dimensions (TFP-144V) Rev. 1.00 May 09, 2008 Page 945 of 954 REJ09B0462-0100...
Page 972 Appendix JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LFBGA176-13x13-0.80 PLBG0176GA-A BP-176/BP-176V 0.45g w S A w S B Dimension in Millimeters Reference Symbol 13.0 13.0 0.15 0.20 1.40 0.35 0.40 0.45 0.80 0.45 0.50 0.55 0.08 0.10 9 10 11 12 13 14 15 φ...
Page 973 Appendix JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TFLGA145-9x9-0.65 PTLG0145JB-A 0.15g Dimension in Millimeters Reference Symbol 0.15 0.20 0.65 0.30 0.35 0.40 11 12 13 0.08 φb φ x n 0.20 Figure C.3 Package Dimensions (TLP-145V) Rev. 1.00 May 09, 2008 Page 947 of 954...
Page 974: Treatment Of Unused Pins
Appendix Treatment of Unused Pins The treatments of unused pins are listed in table D.1. Table D.1 Treatment of Unused Pins Pin Name Example of Pin Treatment (Always used as a reset pin) ETRST (Always used as a reset pin) MD2, MD1 (Always used as mode pins) •...
Page 975: Index
Index Numerics Communications protocol ....... 772 Compare-match count mode ....339 16-bit count mode........339 Condition field .......... 53 16-bit cycle measurement timer (TCM) . 291 Condition-code register (CCR) ....37 16-bit timer pulse unit......223 Conversion time ........703 8-bit timer (TMR) ........
Page 976 Framing error.......... 390 LPC interface clock start request .... 639 LSI internal states in each operating mode ............818 General registers ........35 Memory indirect ........57 Mode transition diagram ......817 Module stop mode ........824 H8S/2140B group compatible Multiprocessor communication vector mode ..........
Page 977 Programming/erasing interface FMSR..........472 parameters..........732 FPCS ........... 728 Programming/erasing interface FPEFEQ ..........740 register ............ 726 FPFR ........... 735 Protection..........766 FRBR ..........459 PWM modes ........... 265 FRSR........... 459 FSCR........... 473 FTDAR ..........731 FTHR ..........460 FTSR........... 460 RAM ............
Page 978 SBYCR..........810 Reset exception handling ......91 SCIFCR ..........474 RXI1 ............420 SCMR..........376 SCR ............ 369 Scan mode..........702 SIRQCR..........612 Serial communication interface (SCI)..361 SMR............ 365 Serial communication interface with FIFO SSR............. 372 (SCIF) ............. 455 STCR ............
Page 979 Toggle output.......... 256 User program mode......717, 747 Trace bit............ 36 Trap instruction exception handling ..93 Vector address switching ......144 TRAPA instruction ......56, 93 TXI1 ............420 Watch mode ..........823 Watchdog timer (WDT) ......349 USB 2.0 host/function module (USB) ..429 Watchdog timer mode......
Page 980 Rev. 1.00 May 09, 2008 Page 954 of 954 REJ09B0462-0100...
Page 981 H8S/2112R Group Publication Date: Rev.1.00, May 09, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 982 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 984 H8S/2112R Group Hardware Manual...

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H8s/2112r

Renesas H8S/2100 Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Resets

Section 5 Exception Handling

Section 6 Interrupt Controller

Section 7 Bus Controller (BSC)

Section 8 I/O Ports

Section 9 8-Bit PWM Timer (PWMU)

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 16-Bit Cycle Measurement Timer (TCM)

Section 12 8-Bit Timer (TMR)

Section 13 Watchdog Timer (WDT)

Section 14 Serial Communication Interface (SCI)

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