Table 12.12 Tiorl_0 (Channel 0) - Renesas H8S Series Hardware Manual

Table 12.12 TIORL_0 (channel 0)

Bit 3 Bit 2
IOC3 IOC2
0 0
1
1 0
1
[Legend]
×:
Don't care
Note: * When the BFA bit in TMDR_0 is set to 1and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 1 Bit 1
IOC1 IOC0
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
×
1
× ×
Section 12 16-Bit Timer Pulse Unit (TPU)
TGRC_0
Function TIOCA0 Pin Function
Output Output disabled
compare
Initial output is 0 output
register*
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Input capture Capture input source is TIOCA0 pin
register* Input capture at rising edge
Capture input source is TIOCA0 pin
Input capture at falling edge
Capture input source is TIOCA0 pin
Input capture at both edges
Setting prohibited
Rev. 3.00 Jul. 14, 2005 Page 321 of 986
Description
REJ09B0098-0300