Subclock Waveform Forming Circuit; Clock Select Circuit; Figure 23.8 Subclock Input Timing - Renesas H8S Series Hardware Manual

Section 23 Clock Pulse Generator
EXCL
23.6

Subclock Waveform Forming Circuit

To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform
forming circuit samples the subclock using a divided φ clock. The sampling frequency is set by the
NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
23.7

Clock Select Circuit

The clock select circuit selects the system clock that is used in this LSI.
A clock generated by the oscillator to which the XTAL and EXTAL pins are connected is selected
as a system clock (φ) when returning from high-speed mode, medium-speed mode, sleep mode,
the reset state, or standby mode.
In subactive mode, subsleep mode, or watch mode, a subclock input from the EXCL (ExEXCL)
pin is selected as a system clock when the EXCLE bit in LPWRCR is 1. At this time, on-chip
peripheral modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, I/O ports, and interrupt
controller and their functions operate on the φSUB clock. The count clock and sampling clock for
each timer are divided φSUB clocks.
Rev. 3.00 Jul. 14, 2005 Page 856 of 986
REJ09B0098-0300
t
EXCLH
t
EXCLr

Figure 23.8 Subclock Input Timing

t
EXCLL
× 0.5
V
CC
t
EXCLf