Slave Transmit Operation; Figure 16.23 Sample Flowchart For Slave Transmit Mode - Renesas H8S Series Hardware Manual

16.4.6

Slave Transmit Operation

If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 16.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Read ACKB in ICSR
End
No
of transmission
(ACKB = 1)?
Yes
Clear IRIC in ICCR
Clear ACKE to 0 in ICCR
(ACKB=0 clear)
Set TRS = 0 in ICCR
Read ICDR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
End

Figure 16.23 Sample Flowchart for Slave Transmit Mode

[1], [2] If the slave address matches to the address in the first frame
following the start condition detection and the R/W bit is 1
in slave recieve mode, the mode changes to slave transmit mode.
[3], [5] Set transmit data for the second and subsequent bytes.
[3], [4] Wait for 1 byte to be transmitted.
[4] Determine end of transfer.
[6] Clear IRIC in ICCR
[7] Clear acknowledge bit data
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
2
Section 16 I C Bus Interface (IIC)
Rev. 3.00 Jul. 14, 2005 Page 559 of 986
REJ09B0098-0300