Initialization; Figure 15.25 Receive Data Sampling Timing In Smart Card Interface Mode (When Clock Frequency Is 372 Times The Bit Rate) - Renesas H8S Series Hardware Manual

Section 15 Serial Communication Interface (SCI, IrDA)
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1/2 × 372) × 100 [%] = 49.866%
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode
15.7.5

Initialization

Before starting transmitting and receiving data, initialize the SCI using the following procedure.
Initialization is also necessary before switching from transmission to reception and vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ORER, ERS, and PER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set
the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the
TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high
impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and
TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output
clock pulses.
Rev. 3.00 Jul. 14, 2005 Page 484 of 986
REJ09B0098-0300
372 clock cycles
186 clock
cycles
0 185
Start bit
(When Clock Frequency is 372 Times the Bit Rate)
371
0
D0
371 0
185
D1