Instruction Set; Table 2.1 Instruction Classification - Renesas H8S Series Hardware Manual

2.6

Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function Instructions
Data transfer MOV
POP*
LDM*
MOVFPE*
Arithmetic ADD, SUB, CMP, NEG
operations
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS*
Logic operations AND, OR, XOR, NOT
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Branch B
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
Block data transfer EEPMOV
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. B is the generic name for conditional branch instructions.
CC
3. Cannot be used in this LSI.
4. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
1 1
, PUSH*
5 5
, STM*
3
, MOVTPE*
4
2
* , JMP, BSR, JSR, RTS
CC
3
Rev. 3.00 Jul. 14, 2005 Page 35 of 986
Section 2 CPU
Size Types
B/W/L 5
W/L
L
B
B/W/L 19
B
B/W/L
L
B/W
W/L
B
B/W/L 4
B/W/L 8
B 14
– 5
– 9
– 1
Total: 65
REJ09B0098-0300