Renesas H8S Series Hardware Manual page 467

Bit Bit Name Initial Value R/W
2 CKS2 0
1 CKS1 0
0 CKS0 0
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Description
R/W Clock Select 2 to 0
R/W Selects the clock source to be input to TCNT. The
overflow cycle for φ = 20 MHz and φSUB = 32.768 kHz is
R/W
enclosed in parentheses.
When PSS = 0:
000: φ/2 (frequency: 25.6 µs)
001: φ/64 (frequency: 819.2 µs)
010: φ/128 (frequency: 1.6 ms)
011: φ/512 (frequency: 6.6 ms)
100: φ/2048 (frequency: 26.2 ms)
101: φ/8192 (frequency: 104.9 ms)
110: φ/32768 (frequency: 419.4 ms)
111: φ/131072 (frequency: 1.68 s)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Section 14 Watchdog Timer (WDT)
Rev. 3.00 Jul. 14, 2005 Page 419 of 986
REJ09B0098-0300