Figure 16.33 Icdr Read And Iccr Access Timing In Slave Transmit Mode - Renesas H8S Series Hardware Manual

11. Note on ICDR read and ICCR access in slave transmit mode
2
In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 16.33. However, such read and write operations cause no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
 Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
 Monitor the BC2 to BC0 bit counter in ICMR; when the count is B'000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
SDA
SCL
TRS bit

Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Waveform at problem occurrence
A
R/W
8 9
Address reception
The rise of the 9th clock is detected
ICDR read and ICCR read/write are disabled
(6 system clock period)
Rev. 3.00 Jul. 14, 2005 Page 577 of 986
2
Section 16 I C Bus Interface (IIC)
ICDR write
Bit 7
Data transmission
REJ09B0098-0300