Table 15.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1) - Renesas H8S Series Hardware Manual

Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 and 15.8 show sample N settings in
BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.5
and 15.7 show the maximum bit rates with external clock input.

Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)

4
Bit Rate Error
(bit/s) n N (%)
110 2 70 0.03
150 1 207 0.16
300 1 103 0.16
600 0 207 0.16
1200 0 103 0.16
2400 0 51 0.16
4800 0 25 0.16
9600 0 12 0.16
  
19200
31250 0 3 0.00
  
38400
Rev. 3.00 Jul. 14, 2005 Page 446 of 986
REJ09B0098-0300
Operating Frequency φ (MHz)
4.9152
Error
n N (%) n
2 86 0.31 2
1 255 0.00 2
1 127 0.00 1
0 255 0.00 1
0 127 0.00 0
0 63 0.00 0
0 31 0.00 0
0 15 0.00 0
0 7 0.00 0
0 4 –1.70 0
0 3 0.00 0
5
Error
N (%) n N
88 –0.25 2 106 –0.44
64 0.16 2 77
129 0.16 1 155 0.16
64 0.16 1 77
129 0.16 0 155 0.16
64 0.16 0 77
32 –1.36 0 38
15 1.73 0 19
7 1.73 0 9
4 0.00 0 5
3 1.73 0 4
6 6.144
Error Error
(%) n N (%)
2 108 0.08
0.16 2 79 0.00
1 159 0.00
0.16 1 79 0.00
0 159 0.00
0.16 0 79 0.00
0.16 0 39 0.00
–2.34 0 19 0.00
–2.34 0 9 0.00
0.00 0 5 2.40
–2.34 0 4 0.00